static int
quicc_bfe_enabled(struct scc_softc *sc, struct scc_chan *ch)
{
struct scc_bas *bas;
int unit;
uint16_t val0, val1;
bas = &sc->sc_bas;
unit = ch->ch_nr - 1;
val0 = quicc_read2(bas, QUICC_REG_SCC_TODR(unit));
quicc_write2(bas, QUICC_REG_SCC_TODR(unit), ~val0);
val1 = quicc_read2(bas, QUICC_REG_SCC_TODR(unit));
quicc_write2(bas, QUICC_REG_SCC_TODR(unit), val0);
return (((val0 | val1) == 0x8000) ? 1 : 0);
}
static int
quicc_bfe_ipend(struct scc_softc *sc)
{
struct scc_bas *bas;
struct scc_chan *ch;
int c, ipend;
uint16_t scce;
bas = &sc->sc_bas;
ipend = 0;
for (c = 0; c < 4; c++) {
ch = &sc->sc_chan[c];
if (!ch->ch_enabled)
continue;
ch->ch_ipend = 0;
mtx_lock_spin(&sc->sc_hwmtx);
scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(c));
quicc_write2(bas, QUICC_REG_SCC_SCCE(c), ~0);
mtx_unlock_spin(&sc->sc_hwmtx);
if (scce & 0x0001)
ch->ch_ipend |= SER_INT_RXREADY;
if (scce & 0x0002)
ch->ch_ipend |= SER_INT_TXIDLE;
if (scce & 0x0004)
ch->ch_ipend |= SER_INT_OVERRUN;
if (scce & 0x0020)
ch->ch_ipend |= SER_INT_BREAK;
/* XXX SIGNALS */
ipend |= ch->ch_ipend;
}
return (ipend);
}
int
quicc_bfe_probe(device_t dev, u_int clock)
{
struct quicc_softc *sc;
uint16_t rev;
sc = device_get_softc(dev);
sc->sc_dev = dev;
if (device_get_desc(dev) == NULL)
device_set_desc(dev,
"Quad integrated communications controller");
sc->sc_rrid = 0;
sc->sc_rtype = SYS_RES_MEMORY;
sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid,
0, ~0, 0, RF_ACTIVE);
if (sc->sc_rres == NULL) {
sc->sc_rrid = 0;
sc->sc_rtype = SYS_RES_IOPORT;
sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype,
&sc->sc_rrid, 0, ~0, 0, RF_ACTIVE);
if (sc->sc_rres == NULL)
return (ENXIO);
}
sc->sc_clock = clock;
/*
* Check that the microcode revision is 0x00e8, as documented
* in the MPC8555E PowerQUICC III Integrated Processor Family
* Reference Manual.
*/
rev = quicc_read2(sc->sc_rres, QUICC_PRAM_REV_NUM);
bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
return ((rev == 0x00e8) ? BUS_PROBE_DEFAULT : ENXIO);
}
