static void
pwm_timer_init(unsigned timer)
{
/* enable the timer clock before we try to talk to it */
modifyreg32(cfg->timers[timer].clock_register, 0, cfg->timers[timer].clock_bit);
/* disable and configure the timer */
rCR1(timer) = 0;
rCR2(timer) = 0;
rSMCR(timer) = 0;
rDIER(timer) = 0;
rCCER(timer) = 0;
rCCMR1(timer) = 0;
rCCMR2(timer) = 0;
rCCER(timer) = 0;
rDCR(timer) = 0;
/* configure the timer to free-run at 1MHz */
rPSC(timer) = cfg->timers[timer].clock_freq / 1000000;
/* and update at the desired rate */
rARR(timer) = 1000000 / cfg->update_rate;
/* generate an update event; reloads the counter and all registers */
rEGR(timer) = GTIM_EGR_UG;
/* note that the timer is left disabled - arming is performed separately */
}
static void
pwm_input_timer_init(unsigned timer)
{
/* enable the timer clock before we try to talk to it */
modifyreg32(pwm_input_timers[timer].clock_register, 0, pwm_input_timers[timer].clock_bit);
/* disable and configure the timer */
rCR1(timer) |= 0;
rCR2(timer) |= 0;
rSMCR(timer) |= 0;
rDIER(timer) |= 0;
rCCER(timer) |= 0;
rCCMR1(timer) |= 0;
rCCMR2(timer) |= 0;
rCCER(timer) |= 0;
rDCR(timer) |= 0;
// if ((pwm_input_timers[timer].base == STM32_TIM1_BASE) || (pwm_input_timers[timer].base == STM32_TIM8_BASE)) {
// /* master output enable = on */
// rBDTR(timer) = ATIM_BDTR_MOE;
// }
/* configure the timer to free-run at 1MHz */
rPSC(timer) |= (pwm_input_timers[timer].clock_freq / 1000000) - 1;
/* run the full span of the counter */
rARR(timer) |= 0xffff;
/* generate an update event; reloads the counter, all registers */
rEGR(timer) |= GTIM_EGR_UG ;
/* enable the timer */
rCR1(timer) |= GTIM_CR1_CEN;
}
static void
input_pwm_timer_init(unsigned timer)
{
/* enable the timer clock before we try to talk to it */
modifyreg32(input_pwm_timers[timer].clock_register, 0, input_pwm_timers[timer].clock_bit);
/* disable and configure the timer */
rCR1(timer) = 0;
rCR2(timer) = 0;
rSMCR(timer) = 0;
rDIER(timer) = 0;
rCCER(timer) = 0;
rCCMR1(timer) = 0;
rCCMR2(timer) = 0;
rCCER(timer) = 0;
rDCR(timer) = 0;
/* configure the timer to free-run at 1MHz */
rPSC(timer) = (input_pwm_timers[timer].clock_freq / 1000000) - 1;
/* run the full span of the counter */
rARR(timer) = 0xffff;
/* generate an update event; reloads the counter, all registers */
rEGR(timer) = GTIM_EGR_UG;
/* enable the timer and disable the update flag event */
rCR1(timer) = GTIM_CR1_UDIS | GTIM_CR1_CEN;
}
static void
pwm_timer_set_rate(unsigned timer, unsigned rate)
{
/* configure the timer to update at the desired rate */
rARR(timer) = 1000000 / rate;
/* generate an update event; reloads the counter and all registers */
rEGR(timer) = GTIM_EGR_UG;
}
static void led_pwm_timer_init_timer(unsigned timer)
{
irqstate_t flags = px4_enter_critical_section();
/* enable the timer clock before we try to talk to it */
modifyreg32(led_pwm_timers[timer].clock_register, 0, led_pwm_timers[timer].clock_bit);
/* disable and configure the timer */
rCR1(timer) = 0;
rCR2(timer) = 0;
rSMCR(timer) = 0;
rDIER(timer) = 0;
rCCER(timer) = 0;
rCCMR1(timer) = 0;
rCCMR2(timer) = 0;
rCCR1(timer) = 0;
rCCR2(timer) = 0;
rCCR3(timer) = 0;
rCCR4(timer) = 0;
rCCER(timer) = 0;
rDCR(timer) = 0;
if ((led_pwm_timers[timer].base == STM32_TIM1_BASE) || (led_pwm_timers[timer].base == STM32_TIM8_BASE)) {
/* master output enable = on */
rBDTR(timer) = ATIM_BDTR_MOE;
}
/* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
* then configure the timer to free-run at 1MHz.
* Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly.
*/
rPSC(timer) = (led_pwm_timers[timer].clock_freq / 1000000) - 1;
/* configure the timer to update at the desired rate */
rARR(timer) = (1000000 / LED_PWM_RATE) - 1;
/* generate an update event; reloads the counter and all registers */
rEGR(timer) = GTIM_EGR_UG;
px4_leave_critical_section(flags);
}
void
led_pwm_servo_arm(bool armed)
{
/* iterate timers and arm/disarm appropriately */
for (unsigned i = 0; i < arraySize(led_pwm_timers); i++) {
if (led_pwm_timers[i].base != 0) {
if (armed) {
/* force an update to preload all registers */
rEGR(i) = GTIM_EGR_UG;
/* arm requires the timer be enabled */
rCR1(i) |= GTIM_CR1_CEN | GTIM_CR1_ARPE;
} else {
rCR1(i) = 0;
}
}
}
}
void
up_pwm_servo_arm(bool armed)
{
/* iterate timers and arm/disarm appropriately */
for (unsigned i = 0; i < PWM_SERVO_MAX_TIMERS; i++) {
if (pwm_timers[i].base != 0) {
if (armed) {
/* force an update to preload all registers */
rEGR(i) = GTIM_EGR_UG;
/* arm requires the timer be enabled */
rCR1(i) |= GTIM_CR1_CEN | GTIM_CR1_ARPE;
} else {
// XXX This leads to FMU PWM being still active
// but uncontrollable. Just disable the timer
// and risk a runt.
///* on disarm, just stop auto-reload so we don't generate runts */
//rCR1(i) &= ~GTIM_CR1_ARPE;
rCR1(i) = 0;
}
}
}
}
static int set_timer(unsigned timer)
{
/* enable the timer clock before we try to talk to it */
modifyreg32(input_timers[timer].clock_register, 0, input_timers[timer].clock_bit);
if(timer == 3) //timer 8
{
ArCR1(timer) |= 0;
ArCR2(timer) |= 0;
ArSMCR(timer) |= 0;
ArDIER(timer) |= 0;
ArCCER(timer) |= 0;
ArCCMR1(timer) |= 0;
ArCCMR2(timer) |= 0;
ArCCER(timer) |= 0;
ArDCR(timer) |= 0;
/* configure the timer to free-run at 1MHz */
ArPSC(timer) = (input_timers[timer].clock_freq / 1000000) - 1;
if (timer == 2)
ArBDTR(timer) |= 0;
/* run the full span of the counter */
ArARR(timer) |= 0xffff;
}
else
{ /* disable and configure the timer */
rCR1(timer) |= 0;
rCR2(timer) |= 0;
rSMCR(timer) |= 0;
rDIER(timer) |= 0;
rCCER(timer) |= 0;
rCCMR1(timer) |= 0;
rCCMR2(timer) |= 0;
rCCER(timer) |= 0;
rDCR(timer) |= 0;
/* configure the timer to free-run at 1MHz */
rPSC(timer) |= (input_timers[timer].clock_freq / 1000000) - 1;
rARR(timer) |= 0xffff;
}
switch (timer)
{
case 0: //timer 14 - channel 1
rCCMR1(timer) |= ((GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC1S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC1F_SHIFT));
rCCMR2(timer) |= 0;
rCCER(timer) |= (GTIM_CCER_CC1E|GTIM_CCER_CC1P|GTIM_CCER_CC1NP);
rDIER(timer) |= GTIM_DIER_CC1IE;
break;
case 1: //timer 12 -channel -1 &2
rCCMR1(timer) |= ((GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC1S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC1F_SHIFT)|(GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC2S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC1F_SHIFT));
rCCMR2(timer) |= 0;
rCCER(timer) |= (GTIM_CCER_CC1E|GTIM_CCER_CC2E|GTIM_CCER_CC1P|GTIM_CCER_CC1NP|GTIM_CCER_CC2P|GTIM_CCER_CC2NP);
rDIER(timer) |= (GTIM_DIER_CC1IE|GTIM_DIER_CC2IE);
break;
case 2://timer 13 - channel 1
rCCMR1(timer) |= ((GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC1S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC1F_SHIFT));
rCCMR2(timer) |= 0;
rCCER(timer) |= (GTIM_CCER_CC1E|GTIM_CCER_CC1P|GTIM_CCER_CC1NP);
rDIER(timer) |= GTIM_DIER_CC1IE;
break;
case 3://timer 8 - channel 1&2
ArCCMR1(timer) |= ((ATIM_CCMR_CCS_CCIN1<<ATIM_CCMR1_CC1S_SHIFT)|(ATIM_CCMR_ICF_FCKINT8<<ATIM_CCMR1_IC1F_SHIFT)|(ATIM_CCMR_CCS_CCIN1<<ATIM_CCMR1_CC2S_SHIFT)|(ATIM_CCMR_ICF_FCKINT8<<ATIM_CCMR1_IC2F_SHIFT));
ArCCMR2(timer) |= 0;
ArCCER(timer) |= (ATIM_CCER_CC1E|ATIM_CCER_CC2E|ATIM_CCER_CC1P|ATIM_CCER_CC1NP|ATIM_CCER_CC2P|ATIM_CCER_CC2NP);
ArDIER(timer) |= (ATIM_DIER_CC1IE|ATIM_DIER_CC2IE);
break;
}
if(timer == 3)
{
/* generate an update event; reloads the counter, all registers */
ArEGR(timer) |= ATIM_EGR_UG ;
/* enable the timer */
ArCR1(timer) |= GTIM_CR1_CEN;
}
else
{
/* generate an update event; reloads the counter, all registers */
rEGR(timer) |= GTIM_EGR_UG ;
/* enable the timer */
rCR1(timer) |= GTIM_CR1_CEN;
}
}
static void
input_pwm_timer_init(unsigned timer)
{
/* enable the timer clock before we try to talk to it */
modifyreg32(input_pwm_timers[timer].clock_register, 0, input_pwm_timers[timer].clock_bit);
/* disable and configure the timer */
rCR1(timer) = 0;
rCR2(timer) = 0;
rSMCR(timer) = 0;
rDIER(timer) = 0;
rCCER(timer) = 0;
rCCMR1(timer) = 0;
rCCMR2(timer) = 0;
rCCER(timer) = 0;
rDCR(timer) = 0;
/* claim our interrupt vector */
//irq_attach(input_pwm_timers[timer].irq_vector, input_pwm_tim_isr);
// if ((input_pwm_timers[timer].base == STM32_TIM1_BASE) || (pwm_timers[timer].base == STM32_TIM8_BASE)) {
// /* master output enable = on */
// rBDTR(timer) = ATIM_BDTR_MOE;
// }
/* configure the timer to free-run at 1MHz */
rPSC(timer) = (input_pwm_timers[timer].clock_freq / 1000000) - 1;
/* run the full span of the counter */
rARR(timer) = 0xffff;
/* generate an update event; reloads the counter, all registers */
rEGR(timer) = GTIM_EGR_UG;
/* note that the timer is left disabled - arming is performed separately */
/* disable and configure the timer */
//rCR1 = 0;
//rCR2 = 0;
//rSMCR = 0;
//rDIER = DIER_HRT | DIER_PPM;
//rCCER = 0; /* unlock CCMR* registers */
//rCCMR1 = CCMR1_PPM;
//rCCMR2 = CCMR2_PPM;
//rCCER = CCER_PPM;
//rDCR = 0;
/* configure the timer to free-run at 1MHz */
//rPSC = (RC_TIMER_CLOCK / 1000000) - 1; /* this really only works for whole-MHz clocks */
/* set an initial capture a little ways off */
//rCCR_HRT = 1000;
/* enable the timer and disable the update flag event */
rCR1(timer) = GTIM_CR1_UDIS | GTIM_CR1_CEN;
/* enable interrupts */
//up_enable_irq(input_pwm_timers[timer].irq_vector);
}