//mean start the SystemTick ISR timer.
//here the test board I use has a 16 MHZ oscillator
//modify it if you have a different board and want a different
//SystemTick ISR frequency
LOCAL void portStartSystemTimer( void )
{
rOut(rSysTickLoad,(CPU_FREQUENCY/1000)-1); /* set reload register */
portNVICSetPriority(-1,1u<<4-1); /* set Priority for Cortex-M0 System Interrupts */
rOut(rSysTickVal,0);
rOut(rSysTickCtrl,(1u<<2)|(1u<<1)|(1u<<0)); /* Enable SysTick IRQ and SysTick Timer */
}
// for printf
EXPORT int putchar( int c )
{
/* Wait for the transmitter to be ready */
if('\n' == c)
{
while ( 0u == (rIn(rUART0_SR) & (1u<<9))) ;
rOut(rUART0_THR,'\r');
}
while ( 0u == (rIn(rUART0_SR) & (1u<<9))) ;
rOut(rUART0_THR,c);
return c;
}
void SkColorCubeFilter::filterSpan(const SkPMColor src[], int count, SkPMColor dst[]) const {
const int* colorToIndex[2];
const SkScalar* colorToFactors[2];
const SkScalar* colorToScalar;
fCache.getProcessingLuts(&colorToIndex, &colorToFactors, &colorToScalar);
const int dim = fCache.cubeDimension();
SkColor* colorCube = (SkColor*)fCubeData->data();
for (int i = 0; i < count; ++i) {
SkColor inputColor = SkUnPreMultiply::PMColorToColor(src[i]);
uint8_t r = SkColorGetR(inputColor);
uint8_t g = SkColorGetG(inputColor);
uint8_t b = SkColorGetB(inputColor);
uint8_t a = SkColorGetA(inputColor);
SkScalar rOut(0), gOut(0), bOut(0);
for (int x = 0; x < 2; ++x) {
for (int y = 0; y < 2; ++y) {
for (int z = 0; z < 2; ++z) {
SkColor lutColor = colorCube[colorToIndex[x][r] +
(colorToIndex[y][g] +
colorToIndex[z][b] * dim) * dim];
SkScalar factor = colorToFactors[x][r] *
colorToFactors[y][g] *
colorToFactors[z][b];
rOut += colorToScalar[SkColorGetR(lutColor)] * factor;
gOut += colorToScalar[SkColorGetG(lutColor)] * factor;
bOut += colorToScalar[SkColorGetB(lutColor)] * factor;
}
}
}
const SkScalar aOut = SkIntToScalar(a);
dst[i] = SkPackARGB32(a,
SkScalarRoundToInt(rOut * aOut),
SkScalarRoundToInt(gOut * aOut),
SkScalarRoundToInt(bOut * aOut));
}
}
bool Circuit::parseLine(std::string line)
{
std::regex sWire("\\s*(wire|input|output) +(\\w+)\\s*;\\s*");
std::regex mWire("\\s*(wire|input|output)\\s+\\[(\\d+)\\:(\\d+)\\]\\s*(\\w+)\\s*;\\s*");
std::regex rGate("\\s*(\\w+)\\s+(\\w+)\\s*\\(\\s*");
std::regex in1("\\s*.(A)\\((\\w+\\[\\d+\\]|\\w+)\\)\\s*,\\s*");
std::regex in2("\\s*.(B|D)\\((\\w+\\[\\d+\\]|\\w+)\\)\\s*,\\s*");
std::regex rOut("\\s*.(Y|Q)\\((\\w+\\[\\d+\\]|\\w+)\\)\\s*");
std::regex assign1("\\s*assign\\s+(\\w+\\[\\d+\\]|\\w+)\\s+\\=\\s+(\\w+\\[\\d+\\]|\\w+)\\s*;\\s*");
std::smatch results;
if(std::regex_match(line, results, sWire))
{
//std::cout << results.str(1) <<" "<< results.str(2) << std::endl;
w = new wire(results.str(2), results.str(1));
if(results.str(1) != "wire")
{
g = new gate(results.str(2), results.str(1));
if(results.str(1) == "input")
{
g->setIn1("root");
g->setOut(results.str(2));
w->setWSource(g);
wireMap["root"]->setWDestination(g);
}
else
{
g->setIn1(results.str(2));
w->setWDestination(g);
}
gateMap.insert(std::pair<std::string, gate*> (results.str(2), g));
}
wireMap.insert(std::pair<std::string, wire*> (results.str(2), w));
}
else if (std::regex_match(line, results, mWire))
{
//std::cout << results.str(1) << " bus " <<results.str(2) << ": "<< results.str(3) << ' '<< results.str(4) << std::endl;
for(int i = std::atoi(results.str(3).c_str()); i <= std::atoi(results.str(2).c_str()); i++)
{
std::string x = results.str(4);
x += '[' + std::to_string(i) + ']';
w = new wire(x, results.str(1));
if(results.str(1) != "wire")
{
g = new gate(x, results.str(1));
if(results.str(1) == "input")
{
g->setIn1("root");
g->setOut(x);
w->setWSource(g);
wireMap["root"]->setWDestination(g);
gateMap.insert(std::pair<std::string, gate*> (x, g));
}
else
{
g->setIn1(x);
w->setWDestination(g);
}
}
wireMap.insert(std::pair<std::string, wire*>(x, w));
}
}
else if (std::regex_match(line, results, rGate))
{
pGate2 = pGate = results.str(2);
//std::cout << "\nGate " << results.str(1) << ' ' <<results.str(2) << std::endl;
if(results.str(1) == "DFFPOSX1")
{
pGate += "_input";
pGate2 += "_output";
g = new gate(pGate, results.str(1));
g->setIn1("root");
wireMap["root"]->setWDestination(g);
gateMap.insert(std::pair<std::string, gate*> (pGate, g));
gateMap[pGate]->setIsFlip(true);
gateMap[pGate]->setFlipIn(true);
g = new gate(pGate2, results.str(1));
g->setFlipIn(true);
gateMap.insert(std::pair<std::string, gate*> (pGate2, g));
gateMap[pGate2]->setIsFlip(true);
gateMap[pGate2]->setFlipIn(false);
}
else
{
g = new gate(results.str(2), results.str(1));
g->setFlipIn(false);
gateMap.insert(std::pair<std::string, gate*> (results.str(2), g));
}
}
else if (std::regex_match(line, results, in1))
{
//std::cout<<"InputPin1: "<< results.str(2) << std::endl;
gateMap[pGate2]->setIn1(results.str(2));
wireMap[results.str(2)]->setWDestination(gateMap[pGate2]);
}
else if (std::regex_match(line, results, in2))
{
//std::cout<<"InputPin2: "<< results.str(2) << std::endl;
gateMap[pGate2]->setIn2(results.str(2));
wireMap[results.str(2)]->setWDestination(gateMap[pGate2]);
}
else if (std::regex_match(line, results, rOut))
{
//std::cout<<"OutputPin: "<< results.str(2) << std::endl;
gateMap[pGate]->setOut(results.str(2));
wireMap[results.str(2)]->setWSource(gateMap[pGate]);
}
else if (std::regex_match(line, results, assign1))
{
//std::cout<<"Assign: "<< results.str(1) << " to" << results.str(2) <<std::endl;
wire *temp1, *temp2;
temp1 = wireMap[results.str(1)];
temp2 = wireMap[results.str(2)];
temp1->setAssign(temp2);
}
else return false;
return true;
}
EXPORT void portOsStartupHook(void)
{
//=========== See SAM3S.h
// Disable Watch Dog, WDT_MR
rOut(rWDT_MR,1u<<15);
/* Set 3 FWS for Embedded Flash Access */
rOut(rEEFC_FMR,(0xFu<<8)& (3<<8));
//=========== Init System Clock To 64MHZ
// See pmc_init() of uTenux
rOut(rCKGR_MOR,0x01370809); /*crystal_init*/
while(0u == (rIn(rPMC_SR)&0x01)); /*wait_stabilized*/
rOut(rCKGR_PLLAR,0x200f0103); /* set_pllar */
while(0u == (rIn(rPMC_SR)&0x02)); /* set_pllar_delay */
rOut(rPMC_MCKR,0x00000001); /* set_mck */
while(0u == (rIn(rPMC_SR)&0x08)); /* set_mckr_delay */
rOut(rPMC_MCKR,0x00000002); /* enable_plla */
while(0u == (rIn(rPMC_SR)&0x08)); /* enable_plla_delay */
//========== Uart0 initialize see uart_init() of uTenux
rOut(rPIO_PDR,(0x01 << 9 | 0x01 << 10 )); /* set to peripheral mode for UART0 transmit/receive */
rOut(rPMC_PCER,1u<<8); /* UART0 clock enable */
rOut(rUART0_CR,0xCu); /* Asynchronous Mode,115200bps, 8bit, non-parity, 1 stop bit */
rOut(rUART0_IDR,0xFFFFFFFF);
rOut(rUART0_BRGR,0x22); /* CD = MCLK/(baud*16) = 34.00(115200bps) MCLK=64MHz */
rOut(rUART0_MR,0x0800);
rOut(rPERIPH_PTCR,0x0800); /* Disable DMA channel */
rOut(rUART0_CR,0x50); /* Enable receiver and transmitter */
portStartSystemTimer();
}
