/* XXX what's up with name? */
struct pipe_buffer* radeon_buffer_from_handle(struct drm_api* api,
struct pipe_screen* screen,
const char* name,
unsigned handle)
{
struct radeon_bo_manager* bom =
((struct radeon_winsys*)screen->winsys)->priv->bom;
struct radeon_pipe_buffer* radeon_buffer;
struct radeon_bo* bo = NULL;
bo = radeon_bo_open(bom, handle, 0, 0, 0, 0);
if (bo == NULL) {
return NULL;
}
radeon_buffer = CALLOC_STRUCT(radeon_pipe_buffer);
if (radeon_buffer == NULL) {
radeon_bo_unref(bo);
return NULL;
}
pipe_reference_init(&radeon_buffer->base.reference, 1);
radeon_buffer->base.screen = screen;
radeon_buffer->base.usage = PIPE_BUFFER_USAGE_PIXEL;
radeon_buffer->bo = bo;
return &radeon_buffer->base;
}
/**
* Create a new mipmap tree, calculate its layout and allocate memory.
*/
radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels,
GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
{
radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
"%s(%p) new tree is %p.\n",
__func__, rmesa, mt);
mt->mesaFormat = mesaFormat;
mt->refcount = 1;
mt->target = target;
mt->faces = _mesa_num_tex_faces(target);
mt->baseLevel = baseLevel;
mt->numLevels = numLevels;
mt->width0 = width0;
mt->height0 = height0;
mt->depth0 = depth0;
mt->tilebits = tilebits;
calculate_miptree_layout(rmesa, mt);
mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
0, mt->totalsize, 1024,
RADEON_GEM_DOMAIN_VRAM,
0);
return mt;
}
static __DRIimage *
radeon_create_image(__DRIscreen *screen,
int width, int height, int format,
unsigned int use,
void *loaderPrivate)
{
__DRIimage *image;
radeonScreenPtr radeonScreen = screen->driverPrivate;
image = calloc(1, sizeof *image);
if (image == NULL)
return NULL;
image->dri_format = format;
switch (format) {
case __DRI_IMAGE_FORMAT_RGB565:
image->format = MESA_FORMAT_B5G6R5_UNORM;
image->internal_format = GL_RGB;
image->data_type = GL_UNSIGNED_BYTE;
break;
case __DRI_IMAGE_FORMAT_XRGB8888:
image->format = MESA_FORMAT_B8G8R8X8_UNORM;
image->internal_format = GL_RGB;
image->data_type = GL_UNSIGNED_BYTE;
break;
case __DRI_IMAGE_FORMAT_ARGB8888:
image->format = MESA_FORMAT_B8G8R8A8_UNORM;
image->internal_format = GL_RGBA;
image->data_type = GL_UNSIGNED_BYTE;
break;
default:
free(image);
return NULL;
}
image->data = loaderPrivate;
image->cpp = _mesa_get_format_bytes(image->format);
image->width = width;
image->height = height;
image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp;
image->bo = radeon_bo_open(radeonScreen->bom,
0,
image->pitch * image->height * image->cpp,
0,
RADEON_GEM_DOMAIN_VRAM,
0);
if (image->bo == NULL) {
free(image);
return NULL;
}
return image;
}
/**
* Allocate space for and store data in a buffer object. Any data that was
* previously stored in the buffer object is lost. If data is NULL,
* memory will be allocated, but no copy will occur.
* Called via ctx->Driver.BufferData().
* \return GL_TRUE for success, GL_FALSE if out of memory
*/
static GLboolean
radeonBufferData(struct gl_context * ctx,
GLenum target,
GLsizeiptrARB size,
const GLvoid * data,
GLenum usage,
struct gl_buffer_object *obj)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_buffer_object *radeon_obj = get_radeon_buffer_object(obj);
radeon_obj->Base.Size = size;
radeon_obj->Base.Usage = usage;
if (radeon_obj->bo != NULL) {
radeon_bo_unref(radeon_obj->bo);
radeon_obj->bo = NULL;
}
if (size != 0) {
radeon_obj->bo = radeon_bo_open(radeon->radeonScreen->bom,
0,
size,
32,
RADEON_GEM_DOMAIN_GTT,
0);
if (!radeon_obj->bo)
return GL_FALSE;
if (data != NULL) {
radeon_bo_map(radeon_obj->bo, GL_TRUE);
memcpy(radeon_obj->bo->ptr, data, size);
radeon_bo_unmap(radeon_obj->bo);
}
}
return GL_TRUE;
}
static void radeonBeginQuery(struct gl_context *ctx, struct gl_query_object *q)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_query_object *query = (struct radeon_query_object *)q;
radeon_print(RADEON_STATE, RADEON_NORMAL, "%s: query id %d\n", __FUNCTION__, q->Id);
assert(radeon->query.current == NULL);
if (radeon->dma.flush)
radeon->dma.flush(radeon->glCtx);
if (!query->bo) {
query->bo = radeon_bo_open(radeon->radeonScreen->bom, 0, RADEON_QUERY_PAGE_SIZE, RADEON_QUERY_PAGE_SIZE, RADEON_GEM_DOMAIN_GTT, 0);
}
query->curr_offset = 0;
radeon->query.current = query;
radeon->query.queryobj.dirty = GL_TRUE;
radeon->hw.is_dirty = GL_TRUE;
}
/* Allocates memory, either by resizing the allocation pointed to by mem_struct,
* or by freeing mem_struct (if non-NULL) and allocating a new space. The size
* is measured in bytes, and the offset from the beginning of card space is
* returned.
*/
uint32_t
radeon_legacy_allocate_memory(ScrnInfoPtr pScrn,
void **mem_struct,
int size,
int align,
int domain)
{
ScreenPtr pScreen = screenInfo.screens[pScrn->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t offset = 0;
#ifdef XF86DRM_MODE
if (info->cs) {
struct radeon_bo *video_bo;
if (*mem_struct)
radeon_legacy_free_memory(pScrn, *mem_struct);
video_bo = radeon_bo_open(info->bufmgr, 0, size, align, domain, 0);
*mem_struct = video_bo;
if (!video_bo)
return 0;
return (uint32_t)-1;
}
#endif
#ifdef USE_EXA
if (info->useEXA) {
ExaOffscreenArea *area = *mem_struct;
if (area != NULL) {
if (area->size >= size)
return area->offset;
exaOffscreenFree(pScreen, area);
}
area = exaOffscreenAlloc(pScreen, size, align, TRUE,
NULL, NULL);
*mem_struct = area;
if (area == NULL)
return 0;
offset = area->offset;
}
#endif /* USE_EXA */
#ifdef USE_XAA
if (!info->useEXA) {
FBLinearPtr linear = *mem_struct;
int cpp = info->CurrentLayout.bitsPerPixel / 8;
/* XAA allocates in units of pixels at the screen bpp, so adjust size
* appropriately.
*/
size = (size + cpp - 1) / cpp;
align = (align + cpp - 1) / cpp;
if (linear) {
if(linear->size >= size)
return linear->offset * cpp;
if(xf86ResizeOffscreenLinear(linear, size))
return linear->offset * cpp;
xf86FreeOffscreenLinear(linear);
}
linear = xf86AllocateOffscreenLinear(pScreen, size, align,
NULL, NULL, NULL);
*mem_struct = linear;
if (!linear) {
int max_size;
xf86QueryLargestOffscreenLinear(pScreen, &max_size, align,
PRIORITY_EXTREME);
if (max_size < size)
return 0;
xf86PurgeUnlockedOffscreenAreas(pScreen);
linear = xf86AllocateOffscreenLinear(pScreen, size, align,
NULL, NULL, NULL);
*mem_struct = linear;
if (!linear)
return 0;
}
offset = linear->offset * cpp;
}
#endif /* USE_XAA */
return offset;
}
static GLboolean
do_blit_readpixels(struct gl_context * ctx,
GLint x, GLint y, GLsizei width, GLsizei height,
GLenum format, GLenum type,
const struct gl_pixelstore_attrib *pack, GLvoid * pixels)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
const struct radeon_renderbuffer *rrb = radeon_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer);
const gl_format dst_format = gl_format_and_type_to_mesa_format(format, type);
unsigned dst_rowstride, dst_imagesize, aligned_rowstride, flip_y;
struct radeon_bo *dst_buffer;
GLint dst_x = 0, dst_y = 0;
intptr_t dst_offset;
/* It's not worth if number of pixels to copy is really small */
if (width * height < 100) {
return GL_FALSE;
}
if (dst_format == MESA_FORMAT_NONE ||
!radeon->vtbl.check_blit(dst_format) || !radeon->vtbl.blit) {
return GL_FALSE;
}
if (ctx->_ImageTransferState || ctx->Color._LogicOpEnabled) {
return GL_FALSE;
}
if (pack->SwapBytes || pack->LsbFirst) {
return GL_FALSE;
}
if (pack->RowLength > 0) {
dst_rowstride = pack->RowLength;
} else {
dst_rowstride = width;
}
if (!_mesa_clip_copytexsubimage(ctx, &dst_x, &dst_y, &x, &y, &width, &height)) {
return GL_TRUE;
}
assert(x >= 0 && y >= 0);
aligned_rowstride = get_texture_image_row_stride(radeon, dst_format, dst_rowstride, 0);
dst_rowstride *= _mesa_get_format_bytes(dst_format);
if (_mesa_is_bufferobj(pack->BufferObj) && aligned_rowstride != dst_rowstride)
return GL_FALSE;
dst_imagesize = get_texture_image_size(dst_format,
aligned_rowstride,
height, 1, 0);
if (!_mesa_is_bufferobj(pack->BufferObj))
{
dst_buffer = radeon_bo_open(radeon->radeonScreen->bom, 0, dst_imagesize, 1024, RADEON_GEM_DOMAIN_GTT, 0);
dst_offset = 0;
}
else
{
dst_buffer = get_radeon_buffer_object(pack->BufferObj)->bo;
dst_offset = (intptr_t)pixels;
}
/* Disable source Y flipping for FBOs */
flip_y = (ctx->ReadBuffer->Name == 0);
if (pack->Invert) {
y = rrb->base.Height - height - y;
flip_y = !flip_y;
}
if (radeon->vtbl.blit(ctx,
rrb->bo,
rrb->draw_offset,
rrb->base.Format,
rrb->pitch / rrb->cpp,
rrb->base.Width,
rrb->base.Height,
x,
y,
dst_buffer,
dst_offset,
dst_format,
aligned_rowstride / _mesa_get_format_bytes(dst_format),
width,
height,
0, /* dst_x */
0, /* dst_y */
width,
height,
flip_y))
{
if (!_mesa_is_bufferobj(pack->BufferObj))
{
radeon_bo_map(dst_buffer, 0);
copy_rows(pixels, dst_rowstride, dst_buffer->ptr,
aligned_rowstride, height, dst_rowstride);
radeon_bo_unmap(dst_buffer);
radeon_bo_unref(dst_buffer);
}
return GL_TRUE;
}
if (!_mesa_is_bufferobj(pack->BufferObj))
radeon_bo_unref(dst_buffer);
return GL_FALSE;
}
static Bool
RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
int h, char *dst, int dst_pitch)
{
RINFO_FROM_SCREEN(pSrc->drawable.pScreen);
struct radeon_exa_pixmap_priv *driver_priv;
struct radeon_bo *scratch = NULL;
struct radeon_bo *copy_src;
unsigned size;
uint32_t datatype = 0;
uint32_t src_domain = 0;
uint32_t src_pitch_offset;
unsigned bpp = pSrc->drawable.bitsPerPixel;
uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64);
uint32_t copy_pitch;
uint32_t swap = RADEON_HOST_DATA_SWAP_NONE;
int ret;
Bool flush = FALSE;
Bool r;
if (bpp < 8)
return FALSE;
driver_priv = exaGetPixmapDriverPrivate(pSrc);
if (!driver_priv || !driver_priv->bo)
return FALSE;
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (bpp) {
case 32:
swap = RADEON_HOST_DATA_SWAP_32BIT;
break;
case 16:
swap = RADEON_HOST_DATA_SWAP_16BIT;
break;
}
#endif
/* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
copy_src = driver_priv->bo;
copy_pitch = pSrc->devKind;
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
src_domain = radeon_bo_get_src_domain(driver_priv->bo);
if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
src_domain = 0;
else /* A write may be scheduled */
flush = TRUE;
}
if (!src_domain)
radeon_bo_is_busy(driver_priv->bo, &src_domain);
if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM)
goto copy;
}
size = scratch_pitch * h;
scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
if (scratch == NULL) {
goto copy;
}
radeon_cs_space_reset_bos(info->cs);
radeon_add_pixmap(info->cs, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, RADEON_GEM_DOMAIN_GTT);
ret = radeon_cs_space_check(info->cs);
if (ret) {
goto copy;
}
RADEONGetDatatypeBpp(pSrc->drawable.bitsPerPixel, &datatype);
RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset);
RADEON_SWITCH_TO_2D();
RADEONBlitChunk(pScrn, driver_priv->bo, scratch, datatype, src_pitch_offset,
scratch_pitch << 16, x, y, 0, 0, w, h,
RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT,
RADEON_GEM_DOMAIN_GTT);
copy_src = scratch;
copy_pitch = scratch_pitch;
flush = TRUE;
copy:
if (flush)
FLUSH_RING();
ret = radeon_bo_map(copy_src, 0);
if (ret) {
ErrorF("failed to map pixmap: %d\n", ret);
r = FALSE;
goto out;
}
r = TRUE;
w *= bpp / 8;
if (copy_src == driver_priv->bo)
size = y * copy_pitch + x * bpp / 8;
else
size = 0;
while (h--) {
RADEONCopySwap((uint8_t*)dst, copy_src->ptr + size, w, swap);
size += copy_pitch;
dst += dst_pitch;
}
radeon_bo_unmap(copy_src);
out:
if (scratch)
radeon_bo_unref(scratch);
return r;
}
static Bool
RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
char *src, int src_pitch)
{
ScreenPtr pScreen = pDst->drawable.pScreen;
RINFO_FROM_SCREEN(pScreen);
struct radeon_exa_pixmap_priv *driver_priv;
struct radeon_bo *scratch = NULL;
struct radeon_bo *copy_dst;
unsigned char *dst;
unsigned size;
uint32_t datatype = 0;
uint32_t dst_domain;
uint32_t dst_pitch_offset;
unsigned bpp = pDst->drawable.bitsPerPixel;
uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64);
uint32_t copy_pitch;
uint32_t swap = RADEON_HOST_DATA_SWAP_NONE;
int ret;
Bool flush = TRUE;
Bool r;
int i;
if (bpp < 8)
return FALSE;
driver_priv = exaGetPixmapDriverPrivate(pDst);
if (!driver_priv || !driver_priv->bo)
return FALSE;
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (bpp) {
case 32:
swap = RADEON_HOST_DATA_SWAP_32BIT;
break;
case 16:
swap = RADEON_HOST_DATA_SWAP_16BIT;
break;
}
#endif
/* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
!(dst_domain & RADEON_GEM_DOMAIN_VRAM))
goto copy;
}
/* use cpu copy for fast fb access */
if (info->is_fast_fb)
goto copy;
}
size = scratch_pitch * h;
scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
if (scratch == NULL) {
goto copy;
}
radeon_cs_space_reset_bos(info->cs);
radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
radeon_cs_space_add_persistent_bo(info->cs, scratch, RADEON_GEM_DOMAIN_GTT, 0);
ret = radeon_cs_space_check(info->cs);
if (ret) {
goto copy;
}
copy_dst = scratch;
copy_pitch = scratch_pitch;
flush = FALSE;
copy:
if (flush)
radeon_cs_flush_indirect(pScrn);
ret = radeon_bo_map(copy_dst, 0);
if (ret) {
r = FALSE;
goto out;
}
r = TRUE;
size = w * bpp / 8;
dst = copy_dst->ptr;
if (copy_dst == driver_priv->bo)
dst += y * copy_pitch + x * bpp / 8;
for (i = 0; i < h; i++) {
RADEONCopySwap(dst + i * copy_pitch, (uint8_t*)src, size, swap);
src += src_pitch;
}
radeon_bo_unmap(copy_dst);
if (copy_dst == scratch) {
RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype);
RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset);
RADEON_SWITCH_TO_2D();
RADEONBlitChunk(pScrn, scratch, driver_priv->bo, datatype, scratch_pitch << 16,
dst_pitch_offset, 0, 0, x, y, w, h,
RADEON_GEM_DOMAIN_GTT, RADEON_GEM_DOMAIN_VRAM);
}
out:
if (scratch)
radeon_bo_unref(scratch);
return r;
}
/**
* Called via glRenderbufferStorageEXT() to set the format and allocate
* storage for a user-created renderbuffer.
*/
static GLboolean
radeon_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
GLenum internalFormat,
GLuint width, GLuint height)
{
struct radeon_context *radeon = RADEON_CONTEXT(ctx);
struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
GLboolean software_buffer = GL_FALSE;
int cpp;
radeon_print(RADEON_TEXTURE, RADEON_TRACE,
"%s(%p, rb %p) \n",
__func__, ctx, rb);
ASSERT(rb->Name != 0);
switch (internalFormat) {
case GL_R3_G3_B2:
case GL_RGB4:
case GL_RGB5:
rb->Format = _dri_texformat_rgb565;
rb->DataType = GL_UNSIGNED_BYTE;
cpp = 2;
break;
case GL_RGB:
case GL_RGB8:
case GL_RGB10:
case GL_RGB12:
case GL_RGB16:
rb->Format = _dri_texformat_argb8888;
rb->DataType = GL_UNSIGNED_BYTE;
cpp = 4;
break;
case GL_RGBA:
case GL_RGBA2:
case GL_RGBA4:
case GL_RGB5_A1:
case GL_RGBA8:
case GL_RGB10_A2:
case GL_RGBA12:
case GL_RGBA16:
rb->Format = _dri_texformat_argb8888;
rb->DataType = GL_UNSIGNED_BYTE;
cpp = 4;
break;
case GL_STENCIL_INDEX:
case GL_STENCIL_INDEX1_EXT:
case GL_STENCIL_INDEX4_EXT:
case GL_STENCIL_INDEX8_EXT:
case GL_STENCIL_INDEX16_EXT:
/* alloc a depth+stencil buffer */
rb->Format = MESA_FORMAT_S8_Z24;
rb->DataType = GL_UNSIGNED_INT_24_8_EXT;
cpp = 4;
break;
case GL_DEPTH_COMPONENT16:
rb->Format = MESA_FORMAT_Z16;
rb->DataType = GL_UNSIGNED_SHORT;
cpp = 2;
break;
case GL_DEPTH_COMPONENT:
case GL_DEPTH_COMPONENT24:
case GL_DEPTH_COMPONENT32:
rb->Format = MESA_FORMAT_X8_Z24;
rb->DataType = GL_UNSIGNED_INT;
cpp = 4;
break;
case GL_DEPTH_STENCIL_EXT:
case GL_DEPTH24_STENCIL8_EXT:
rb->Format = MESA_FORMAT_S8_Z24;
rb->DataType = GL_UNSIGNED_INT_24_8_EXT;
cpp = 4;
break;
default:
_mesa_problem(ctx,
"Unexpected format in radeon_alloc_renderbuffer_storage");
return GL_FALSE;
}
rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat);
if (ctx->Driver.Flush)
ctx->Driver.Flush(ctx); /* +r6/r7 */
if (rrb->bo)
radeon_bo_unref(rrb->bo);
if (software_buffer) {
return _mesa_soft_renderbuffer_storage(ctx, rb, internalFormat,
width, height);
}
else {
uint32_t size;
uint32_t pitch = ((cpp * width + 63) & ~63) / cpp;
if (RADEON_DEBUG & RADEON_MEMORY)
fprintf(stderr,"Allocating %d x %d radeon RBO (pitch %d)\n", width,
height, pitch);
size = pitch * height * cpp;
rrb->pitch = pitch * cpp;
rrb->cpp = cpp;
rrb->bo = radeon_bo_open(radeon->radeonScreen->bom,
0,
size,
0,
RADEON_GEM_DOMAIN_VRAM,
0);
rb->Width = width;
rb->Height = height;
return GL_TRUE;
}
}
/* Calculate appropriate tiling and pitch for a pixmap and allocate a BO that
* can hold it.
*/
struct radeon_bo*
radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
int usage_hint, int bitsPerPixel, int *new_pitch,
struct radeon_surface *new_surface, uint32_t *new_tiling)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
int pitch, base_align;
uint32_t size, heighta;
int cpp = bitsPerPixel / 8;
uint32_t tiling = 0;
struct radeon_surface surface;
struct radeon_bo *bo;
int domain = RADEON_GEM_DOMAIN_VRAM;
if (usage_hint) {
if (info->allowColorTiling) {
if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MACRO)
tiling |= RADEON_TILING_MACRO;
if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MICRO)
tiling |= RADEON_TILING_MICRO;
}
if (usage_hint & RADEON_CREATE_PIXMAP_DEPTH)
tiling |= RADEON_TILING_MACRO | RADEON_TILING_MICRO;
#ifdef CREATE_PIXMAP_USAGE_SHARED
if ((usage_hint & 0xffff) == CREATE_PIXMAP_USAGE_SHARED) {
tiling = 0;
domain = RADEON_GEM_DOMAIN_GTT;
}
#endif
}
/* Small pixmaps must not be macrotiled on R300, hw cannot sample them
* correctly because samplers automatically switch to macrolinear. */
if (info->ChipFamily >= CHIP_FAMILY_R300 &&
info->ChipFamily <= CHIP_FAMILY_RS740 &&
(tiling & RADEON_TILING_MACRO) &&
!RADEONMacroSwitch(width, height, bitsPerPixel, tiling,
info->ChipFamily >= CHIP_FAMILY_RV350)) {
tiling &= ~RADEON_TILING_MACRO;
}
heighta = RADEON_ALIGN(height, drmmode_get_height_align(pScrn, tiling));
pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, cpp, tiling)) * cpp;
base_align = drmmode_get_base_align(pScrn, cpp, tiling);
size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE);
memset(&surface, 0, sizeof(struct radeon_surface));
if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
if (width) {
surface.npix_x = width;
/* need to align height to 8 for old kernel */
surface.npix_y = RADEON_ALIGN(height, 8);
surface.npix_z = 1;
surface.blk_w = 1;
surface.blk_h = 1;
surface.blk_d = 1;
surface.array_size = 1;
surface.last_level = 0;
surface.bpe = cpp;
surface.nsamples = 1;
if (height < 128) {
/* disable 2d tiling for small surface to work around
* the fact that ddx align height to 8 pixel for old
* obscure reason i can't remember
*/
tiling &= ~RADEON_TILING_MACRO;
}
surface.flags = RADEON_SURF_SCANOUT;
/* we are requiring a recent enough libdrm version */
surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
if ((tiling & RADEON_TILING_MICRO)) {
surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
}
if ((tiling & RADEON_TILING_MACRO)) {
surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
}
if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) {
surface.flags |= RADEON_SURF_ZBUFFER;
surface.flags |= RADEON_SURF_SBUFFER;
}
if (radeon_surface_best(info->surf_man, &surface)) {
return NULL;
}
if (radeon_surface_init(info->surf_man, &surface)) {
return NULL;
}
size = surface.bo_size;
base_align = surface.bo_alignment;
pitch = surface.level[0].pitch_bytes;
tiling = 0;
switch (surface.level[0].mode) {
case RADEON_SURF_MODE_2D:
tiling |= RADEON_TILING_MACRO;
tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
break;
case RADEON_SURF_MODE_1D:
tiling |= RADEON_TILING_MICRO;
break;
default:
break;
}
}
}
bo = radeon_bo_open(info->bufmgr, 0, size, base_align,
domain, 0);
if (bo && tiling && radeon_bo_set_tiling(bo, tiling, pitch) == 0)
*new_tiling = tiling;
*new_surface = surface;
*new_pitch = pitch;
return bo;
}
