static void r600_flush_vgt_streamout(struct r600_common_context *rctx) { struct radeon_winsys_cs *cs = rctx->gfx.cs; unsigned reg_strmout_cntl; /* The register is at different places on different ASICs. */ if (rctx->chip_class >= CIK) { reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL; } else if (rctx->chip_class >= EVERGREEN) { reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL; } else { reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL; } if (rctx->chip_class >= CIK) { radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0); } else { radeon_set_config_reg(cs, reg_strmout_cntl, 0); } radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ radeon_emit(cs, reg_strmout_cntl >> 2); /* register */ radeon_emit(cs, 0); radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */ radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */ radeon_emit(cs, 4); /* poll interval */ }
static void si_write_harvested_raster_configs(struct radv_physical_device *physical_device, struct radeon_winsys_cs *cs, unsigned raster_config, unsigned raster_config_1) { unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1); unsigned num_se = MAX2(physical_device->rad_info.max_se, 1); unsigned rb_mask = physical_device->rad_info.enabled_rb_mask; unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16); unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2); unsigned rb_per_se = num_rb / num_se; unsigned se_mask[4]; unsigned se; se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; assert(num_se == 1 || num_se == 2 || num_se == 4); assert(sh_per_se == 1 || sh_per_se == 2); assert(rb_per_pkr == 1 || rb_per_pkr == 2); /* XXX: I can't figure out what the *_XSEL and *_YSEL * fields are for, so I'm leaving them as their default * values. */ if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || (!se_mask[2] && !se_mask[3]))) { raster_config_1 &= C_028354_SE_PAIR_MAP; if (!se_mask[0] && !se_mask[1]) { raster_config_1 |= S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3); } else { raster_config_1 |= S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0); } } for (se = 0; se < num_se; se++) { unsigned raster_config_se = raster_config; unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); unsigned pkr1_mask = pkr0_mask << rb_per_pkr; int idx = (se / 2) * 2; if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { raster_config_se &= C_028350_SE_MAP; if (!se_mask[idx]) { raster_config_se |= S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3); } else { raster_config_se |= S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0); } } pkr0_mask &= rb_mask; pkr1_mask &= rb_mask; if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { raster_config_se &= C_028350_PKR_MAP; if (!pkr0_mask) { raster_config_se |= S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3); } else { raster_config_se |= S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0); } } if (rb_per_se >= 2) { unsigned rb0_mask = 1 << (se * rb_per_se); unsigned rb1_mask = rb0_mask << 1; rb0_mask &= rb_mask; rb1_mask &= rb_mask; if (!rb0_mask || !rb1_mask) { raster_config_se &= C_028350_RB_MAP_PKR0; if (!rb0_mask) { raster_config_se |= S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3); } else { raster_config_se |= S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0); } } if (rb_per_se > 2) { rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); rb1_mask = rb0_mask << 1; rb0_mask &= rb_mask; rb1_mask &= rb_mask; if (!rb0_mask || !rb1_mask) { raster_config_se &= C_028350_RB_MAP_PKR1; if (!rb0_mask) { raster_config_se |= S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3); } else { raster_config_se |= S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0); } } } } /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ if (physical_device->rad_info.chip_class < CIK) radeon_set_config_reg(cs, GRBM_GFX_INDEX, SE_INDEX(se) | SH_BROADCAST_WRITES | INSTANCE_BROADCAST_WRITES); else radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1)); radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); if (physical_device->rad_info.chip_class >= CIK) radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ if (physical_device->rad_info.chip_class < CIK) radeon_set_config_reg(cs, GRBM_GFX_INDEX, SE_BROADCAST_WRITES | SH_BROADCAST_WRITES | INSTANCE_BROADCAST_WRITES); else radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1)); }