static void __init jmr3927_mem_setup(void) { set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); _machine_restart = jmr3927_machine_restart; { unsigned int conf; #ifdef DO_WRITE_THROUGH int mips_config_cwfon = 0; int mips_config_wbon = 0; #else int mips_config_cwfon = 1; int mips_config_wbon = 1; #endif conf = read_c0_conf(); conf &= ~(TX39_CONF_WBON | TX39_CONF_CWFON); conf |= mips_config_wbon ? TX39_CONF_WBON : 0; conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; write_c0_conf(conf); write_c0_cache(0); } jmr3927_board_init(); tx3927_sio_init(0, 1 << 1); }
static void r39xx_wait(void) { local_irq_disable(); if (!need_resched()) write_c0_conf(read_c0_conf() | TX39_CONF_HALT); local_irq_enable(); }
/* * Probe whether cpu has config register by trying to play with * alternate cache bit and see whether it matters. * It's used by cpu_probe to distinguish between R3000A and R3081. */ static inline int cpu_has_confreg(void) { #ifdef CONFIG_CPU_R3000 extern unsigned long r3k_cache_size(unsigned long); unsigned long size1, size2; unsigned long cfg = read_c0_conf(); size1 = r3k_cache_size(ST0_ISC); write_c0_conf(cfg ^ R30XX_CONF_AC); size2 = r3k_cache_size(ST0_ISC); write_c0_conf(cfg); return size1 != size2; #else return 0; #endif }
static void r3081_wait(void) { unsigned long cfg = read_c0_conf(); write_c0_conf(cfg | R30XX_CONF_HALT); }
void __init tx3927_setup(void) { int i; /* SDRAMC are configured by PROM */ /* ROMC */ tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; /* CCFG */ /* enable Timeout BusError */ if (jmr3927_ccfg_toeon) tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; /* clear BusErrorOnWrite flag */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; /* Disable PCI snoop */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; #ifdef DO_WRITE_THROUGH /* Enable PCI SNOOP - with write through only */ tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; #endif /* Pin selection */ tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; tx3927_ccfgptr->pcfg |= TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", tx3927_ccfgptr->crir, tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); /* IRC */ /* disable interrupt control */ tx3927_ircptr->cer = 0; /* mask all IRC interrupts */ tx3927_ircptr->imr = 0; for (i = 0; i < TX3927_NUM_IR / 2; i++) { tx3927_ircptr->ilr[i] = 0; } /* setup IRC interrupt mode (Low Active) */ for (i = 0; i < TX3927_NUM_IR / 8; i++) { tx3927_ircptr->cr[i] = 0; } /* TMR */ /* disable all timers */ for (i = 0; i < TX3927_NR_TMR; i++) { tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE; tx3927_tmrptr(i)->tisr = 0; tx3927_tmrptr(i)->cpra = 0xffffffff; tx3927_tmrptr(i)->itmr = 0; tx3927_tmrptr(i)->ccdr = 0; tx3927_tmrptr(i)->pgmr = 0; } /* DMA */ tx3927_dmaptr->mcr = 0; for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) { /* reset channel */ tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; tx3927_dmaptr->ch[i].ccr = 0; } /* enable DMA */ #ifdef __BIG_ENDIAN tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; #else tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; #endif #ifdef CONFIG_PCI /* PCIC */ printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", tx3927_pcicptr->did, tx3927_pcicptr->vid, tx3927_pcicptr->rid); if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { printk("External\n"); /* XXX */ } else { printk("Internal\n"); /* Reset PCI Bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); /* Disable External PCI Config. Access */ tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; #ifdef __BIG_ENDIAN tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | TX3927_PCIC_LBC_TIBSE | TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; #endif /* LB->PCI mappings */ tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); tx3927_pcicptr->ilbioma = mips_pci_io_base; tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); tx3927_pcicptr->ilbmma = mips_pci_mem_base; tx3927_pcicptr->ipbmma = mips_pci_mem_base; /* PCI->LB mappings */ tx3927_pcicptr->iobas = 0xffffffff; tx3927_pcicptr->ioba = 0; tx3927_pcicptr->tlbioma = 0; tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); tx3927_pcicptr->mba = 0; tx3927_pcicptr->tlbmma = 0; #ifndef JMR3927_INIT_INDIRECT_PCI /* Enable Direct mapping Address Space Decoder */ tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; #endif /* Clear All Local Bus Status */ tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; /* Enable All Local Bus Interrupts */ tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; /* Clear All PCI Status Error */ tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; /* Enable All PCI Status Error Interrupts */ tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; /* PCIC Int => IRC IRQ10 */ tx3927_pcicptr->il = TX3927_IR_PCI; #if 1 /* Target Control (per errata) */ tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; #endif /* Enable Bus Arbiter */ #if 0 tx3927_pcicptr->req_trace = 0x73737373; #endif tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | #if 1 PCI_COMMAND_IO | #endif PCI_COMMAND_PARITY | PCI_COMMAND_SERR; } #endif /* CONFIG_PCI */ /* PIO */ /* PIO[15:12] connected to LEDs */ tx3927_pioptr->dir = 0x0000f000; tx3927_pioptr->maskcpu = 0; tx3927_pioptr->maskext = 0; { unsigned int conf; conf = read_c0_conf(); if (!(conf & TX39_CONF_ICE)) printk("TX3927 I-Cache disabled.\n"); if (!(conf & TX39_CONF_DCE)) printk("TX3927 D-Cache disabled.\n"); else if (!(conf & TX39_CONF_WBON)) printk("TX3927 D-Cache WriteThrough.\n"); else if (!(conf & TX39_CONF_CWFON)) printk("TX3927 D-Cache WriteBack.\n"); else printk("TX3927 D-Cache WriteBack (CWF) .\n"); } }
void __init plat_setup(void) { char *argptr; set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); board_time_init = jmr3927_time_init; board_timer_setup = jmr3927_timer_setup; _machine_restart = jmr3927_machine_restart; _machine_halt = jmr3927_machine_halt; pm_power_off = jmr3927_machine_power_off; /* * IO/MEM resources. */ ioport_resource.start = pci_io_resource.start; ioport_resource.end = pci_io_resource.end; iomem_resource.start = 0; iomem_resource.end = 0xffffffff; /* Reboot on panic */ panic_timeout = 180; { unsigned int conf; conf = read_c0_conf(); } #if 1 /* cache setup */ { unsigned int conf; #ifdef DO_ENABLE_CACHE int mips_ic_disable = 0, mips_dc_disable = 0; #else int mips_ic_disable = 1, mips_dc_disable = 1; #endif #ifdef DO_WRITE_THROUGH int mips_config_cwfon = 0; int mips_config_wbon = 0; #else int mips_config_cwfon = 1; int mips_config_wbon = 1; #endif conf = read_c0_conf(); conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; conf |= mips_config_wbon ? TX39_CONF_WBON : 0; conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; write_c0_conf(conf); write_c0_cache(0); } #endif /* initialize board */ jmr3927_board_init(); argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "toeon")) != NULL) { jmr3927_ccfg_toeon = 1; } argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "ip=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " ip=bootp"); } #ifdef CONFIG_SERIAL_TXX9 { extern int early_serial_txx9_setup(struct uart_port *port); int i; struct uart_port req; for(i = 0; i < 2; i++) { memset(&req, 0, sizeof(req)); req.line = i; req.iotype = UPIO_MEM; req.membase = (char *)TX3927_SIO_REG(i); req.mapbase = TX3927_SIO_REG(i); req.irq = i == 0 ? JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; if (i == 0) req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; req.uartclk = JMR3927_IMCLK; early_serial_txx9_setup(&req); } } #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS1,115200"); } #endif #endif }
void __init tx3927_setup(void) { int i; unsigned int conf; txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE, TX3927_REG_SIZE); /* SDRAMC,ROMC are configured by PROM */ for (i = 0; i < 8; i++) { if (!(tx3927_romcptr->cr[i] & 0x8)) continue; /* disabled */ txx9_ce_res[i].start = (unsigned long)TX3927_ROMC_BA(i); txx9_ce_res[i].end = txx9_ce_res[i].start + TX3927_ROMC_SIZE(i) - 1; request_resource(&iomem_resource, &txx9_ce_res[i]); } /* clocks */ txx9_gbus_clock = txx9_cpu_clock / 2; /* change default value to udelay/mdelay take reasonable time */ loops_per_jiffy = txx9_cpu_clock / HZ / 2; /* CCFG */ /* enable Timeout BusError */ if (txx9_ccfg_toeon) tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; /* clear BusErrorOnWrite flag */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; if (read_c0_conf() & TX39_CONF_WBON) /* Disable PCI snoop */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; else /* Enable PCI SNOOP - with write through only */ tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; /* do reset on watchdog */ tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", tx3927_ccfgptr->crir, tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); /* TMR */ for (i = 0; i < TX3927_NR_TMR; i++) txx9_tmr_init(TX3927_TMR_REG(i)); /* DMA */ tx3927_dmaptr->mcr = 0; for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { /* reset channel */ tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; tx3927_dmaptr->ch[i].ccr = 0; } /* enable DMA */ #ifdef __BIG_ENDIAN tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; #else tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; #endif /* PIO */ __raw_writel(0, &tx3927_pioptr->maskcpu); __raw_writel(0, &tx3927_pioptr->maskext); txx9_gpio_init(TX3927_PIO_REG, 0, 16); conf = read_c0_conf(); if (conf & TX39_CONF_DCE) { if (!(conf & TX39_CONF_WBON)) pr_info("TX3927 D-Cache WriteThrough.\n"); else if (!(conf & TX39_CONF_CWFON)) pr_info("TX3927 D-Cache WriteBack.\n"); else pr_info("TX3927 D-Cache WriteBack (CWF) .\n"); } }
static void r39xx_wait(void) { unsigned long cfg = read_c0_conf(); write_c0_conf(cfg | TX39_CONF_HALT); }
static void __init jmr3927_setup(void) { char *argptr; set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); board_time_init = jmr3927_time_init; board_timer_setup = jmr3927_timer_setup; _machine_restart = jmr3927_machine_restart; _machine_halt = jmr3927_machine_halt; _machine_power_off = jmr3927_machine_power_off; /* * IO/MEM resources. */ ioport_resource.start = pci_io_resource.start; ioport_resource.end = pci_io_resource.end; iomem_resource.start = pci_mem_resource.start; iomem_resource.end = pci_mem_resource.end; /* Reboot on panic */ panic_timeout = 180; { unsigned int conf; conf = read_c0_conf(); } #if 1 /* cache setup */ { unsigned int conf; #ifdef DO_ENABLE_CACHE int mips_ic_disable = 0, mips_dc_disable = 0; #else int mips_ic_disable = 1, mips_dc_disable = 1; #endif #ifdef DO_WRITE_THROUGH int mips_config_cwfon = 0; int mips_config_wbon = 0; #else int mips_config_cwfon = 1; int mips_config_wbon = 1; #endif conf = read_c0_conf(); conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; conf |= mips_config_wbon ? TX39_CONF_WBON : 0; conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; write_c0_conf(conf); write_c0_cache(0); } #endif /* initialize board */ jmr3927_board_init(); argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "toeon")) != NULL) { jmr3927_ccfg_toeon = 1; } argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "ip=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " ip=bootp"); } #ifdef CONFIG_TXX927_SERIAL_CONSOLE argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS1,115200"); } #endif }
static void __init tx3927_setup(void) { int i; #ifdef CONFIG_PCI unsigned long mips_pci_io_base = JMR3927_PCIIO; unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; unsigned long mips_pci_mem_base = JMR3927_PCIMEM; unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ unsigned long mips_pci_io_pciaddr = 0; #endif /* SDRAMC are configured by PROM */ /* ROMC */ tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; /* CCFG */ /* enable Timeout BusError */ if (jmr3927_ccfg_toeon) tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; /* clear BusErrorOnWrite flag */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; /* Disable PCI snoop */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; /* do reset on watchdog */ tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; #ifdef DO_WRITE_THROUGH /* Enable PCI SNOOP - with write through only */ tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; #endif /* Pin selection */ tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; tx3927_ccfgptr->pcfg |= TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", tx3927_ccfgptr->crir, tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); /* TMR */ for (i = 0; i < TX3927_NR_TMR; i++) txx9_tmr_init(TX3927_TMR_REG(i)); /* DMA */ tx3927_dmaptr->mcr = 0; for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { /* reset channel */ tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; tx3927_dmaptr->ch[i].ccr = 0; } /* enable DMA */ #ifdef __BIG_ENDIAN tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; #else tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; #endif #ifdef CONFIG_PCI /* PCIC */ printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", tx3927_pcicptr->did, tx3927_pcicptr->vid, tx3927_pcicptr->rid); if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { printk("External\n"); /* XXX */ } else { printk("Internal\n"); /* Reset PCI Bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); /* Disable External PCI Config. Access */ tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; #ifdef __BIG_ENDIAN tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | TX3927_PCIC_LBC_TIBSE | TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; #endif /* LB->PCI mappings */ tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); tx3927_pcicptr->ilbioma = mips_pci_io_base; tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); tx3927_pcicptr->ilbmma = mips_pci_mem_base; tx3927_pcicptr->ipbmma = mips_pci_mem_base; /* PCI->LB mappings */ tx3927_pcicptr->iobas = 0xffffffff; tx3927_pcicptr->ioba = 0; tx3927_pcicptr->tlbioma = 0; tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); tx3927_pcicptr->mba = 0; tx3927_pcicptr->tlbmma = 0; /* Enable Direct mapping Address Space Decoder */ tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; /* Clear All Local Bus Status */ tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; /* Enable All Local Bus Interrupts */ tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; /* Clear All PCI Status Error */ tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; /* Enable All PCI Status Error Interrupts */ tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; /* PCIC Int => IRC IRQ10 */ tx3927_pcicptr->il = TX3927_IR_PCI; /* Target Control (per errata) */ tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; /* Enable Bus Arbiter */ tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; } #endif /* CONFIG_PCI */ /* PIO */ /* PIO[15:12] connected to LEDs */ __raw_writel(0x0000f000, &tx3927_pioptr->dir); __raw_writel(0, &tx3927_pioptr->maskcpu); __raw_writel(0, &tx3927_pioptr->maskext); txx9_gpio_init(TX3927_PIO_REG, 0, 16); gpio_request(11, "dipsw1"); gpio_request(10, "dipsw2"); { unsigned int conf; conf = read_c0_conf(); if (!(conf & TX39_CONF_ICE)) printk("TX3927 I-Cache disabled.\n"); if (!(conf & TX39_CONF_DCE)) printk("TX3927 D-Cache disabled.\n"); else if (!(conf & TX39_CONF_WBON)) printk("TX3927 D-Cache WriteThrough.\n"); else if (!(conf & TX39_CONF_CWFON)) printk("TX3927 D-Cache WriteBack.\n"); else printk("TX3927 D-Cache WriteBack (CWF) .\n"); } }