static uint64_t reg_read(struct reg_script_context *ctx)
{
const struct reg_script *step = ctx->step;
uint64_t value = 0;
switch (step->id) {
default:
printk(BIOS_ERR,
"ERROR - Unknown register set (0x%08x)!\n",
step->id);
ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
return 0;
case GPE0_REGS:
ctx->display_prefix = "GPE0";
value = reg_gpe0_read(step->reg);
break;
case GPIO_REGS:
ctx->display_prefix = "GPIO";
value = reg_gpio_read(step->reg);
break;
case HOST_BRIDGE:
ctx->display_prefix = "Host Bridge";
value = reg_host_bridge_unit_read(step->reg);
break;
case LEG_GPIO_REGS:
ctx->display_prefix = "Legacy GPIO";
value = reg_legacy_gpio_read(step->reg);
break;
case PCIE_AFE_REGS:
ctx->display_prefix = "PCIe AFE";
value = reg_pcie_afe_read(step->reg);
break;
case RMU_TEMP_REGS:
ctx->display_prefix = "RMU TEMP";
value = reg_rmu_temp_read(step->reg);
break;
case SOC_UNIT_REGS:
ctx->display_prefix = "SOC Unit";
value = reg_soc_unit_read(step->reg);
break;
case USB_PHY_REGS:
ctx->display_prefix = "USB PHY";
value = reg_usb_read(step->reg);
break;
}
return value;
}
static void chip_init(void *chip_info)
{
/* Validate the temperature settings */
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
> PLATFORM_CATASTROPHIC_CLEAR_CELSIUS);
/* Set the temperature settings */
reg_script_run(thermal_init_script);
/* Verify that the thermal configuration is locked */
ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG)
& (TS_LOCK_THRM_CTRL_REGS_ENABLE
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE))
== (TS_LOCK_THRM_CTRL_REGS_ENABLE
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
/* Perform silicon specific init. */
fsp_silicon_init();
}
