static __init int __init ja_pci_init(void)
{
uint32_t enable;
extern int pci_probe_only;
/* PMON will assign PCI resources */
pci_probe_only = 1;
enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
/*
* We require at least one enabled I/O or PCI memory window or we
* will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
*/
if (enable & (0x01 << 9) || enable & (0x01 << 10))
register_pci_controller(&mv_bus0_controller.pcic);
if (enable & (0x01 << 14) || enable & (0x01 << 15))
register_pci_controller(&mv_bus1_controller.pcic);
ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE +
OCELOT_3_PCI_IO_1_SIZE - 1;
iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE +
OCELOT_3_PCI_MEM_1_SIZE - 1;
set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */
return 0;
}
static int __init bcm63xx_pci_init(void)
{
/* adjust global io port range */
ioport_resource.start = BCM_PCI_IO_BASE;
ioport_resource.end = BCM_PCI_IO_BASE + BCM_PCI_IO_SIZE-1;
/* bus 0 */
register_pci_controller(&bcm63xx_controller);
#if defined(CONFIG_BCM96362)
bcm63xx_pci_swhdr_patch();
#endif
#if defined(CONFIG_BCM96816)
PCIEH_BRIDGE_REGS->bridgeOptReg1 |= (PCIE_BRIDGE_OPT_REG1_EN_RD_BE | PCIE_BRIDGE_OPT_REG1_EN_RD_BE_NOSWAP);
#endif
#if defined(CONFIG_BCM96362) || defined(CONFIG_BCM96328)
PCIEH_BRIDGE_REGS->bridgeOptReg1 |= (
PCIE_BRIDGE_OPT_REG1_en_l1_int_status_mask_polarity |
PCIE_BRIDGE_OPT_REG1_en_pcie_bridge_hole_detection |
PCIE_BRIDGE_OPT_REG1_en_rd_reply_be_fix |
PCIE_BRIDGE_OPT_REG1_enable_rd_be_opt);
PCIEH_BRIDGE_REGS->rcInterruptMask |= (
PCIE_BRIDGE_INTERRUPT_MASK_int_a_MASK |
PCIE_BRIDGE_INTERRUPT_MASK_int_b_MASK |
PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK |
PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK );
/* enable credit checking and error checking */
PCIEH_BRIDGE_REGS->bridgeOptReg2 |= ( PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK |
PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK );
#endif
#if defined(CONFIG_BCM96816) || defined(CONFIG_BCM96362) || defined(CONFIG_BCM96328)
/* set device bus/func/func */
PCIEH_BRIDGE_REGS->bridgeOptReg2 |= ((BCM_BUS_PCIE_DEVICE<<PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT) |
PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK );
/* setup class code, as bridge */
PCIEH_BLK_428_REGS->idVal3 &= ~PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK;
PCIEH_BLK_428_REGS->idVal3 |= (PCI_CLASS_BRIDGE_PCI << 8);
/* disable bar0 size */
PCIEH_BLK_404_REGS->config2 &= ~PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK;
/*bus 1 and 2 */
register_pci_controller(&bcm63xx_pcie_controller);
#endif
return 0;
}
static int ltq_pci_probe(struct platform_device *pdev)
{
struct resource *res_cfg, *res_bridge;
pci_clear_flags(PCI_PROBE_ONLY);
res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res_cfg || !res_bridge) {
dev_err(&pdev->dev, "missing memory reources\n");
return -EINVAL;
}
ltq_pci_membase = devm_request_and_ioremap(&pdev->dev, res_bridge);
ltq_pci_mapped_cfg = devm_request_and_ioremap(&pdev->dev, res_cfg);
if (!ltq_pci_membase || !ltq_pci_mapped_cfg) {
dev_err(&pdev->dev, "failed to remap resources\n");
return -ENOMEM;
}
ltq_pci_startup(pdev);
pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
register_pci_controller(&pci_controller);
return 0;
}
void __init plat_setup(void)
{
sni_pcimt_detect();
sni_pcimt_sc_init();
sni_pcimt_time_init();
set_io_port_base(SNI_PORT_BASE);
ioport_resource.end = sni_io_resource.end;
/*
* Setup (E)ISA I/O memory access stuff
*/
isa_slot_offset = 0xb0000000;
#ifdef CONFIG_EISA
EISA_bus = 1;
#endif
sni_resource_init();
board_timer_setup = sni_rm200_pci_timer_setup;
_machine_restart = sni_machine_restart;
_machine_halt = sni_machine_halt;
pm_power_off = sni_machine_power_off;
sni_display_setup();
#ifdef CONFIG_PCI
register_pci_controller(&sni_controller);
#endif
}
static int __init au1x_pci_setup(void)
{
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
if (!virt_io_addr) {
printk(KERN_ERR "Unable to ioremap pci space\n");
return 1;
}
#ifdef CONFIG_DMA_NONCOHERENT
{
/*
* Set the NC bit in controller for Au1500 pre-AC silicon
*/
u32 prid = read_c0_prid();
if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
Au1500_PCI_CFG);
printk("Non-coherent PCI accesses enabled\n");
}
}
#endif
set_io_port_base(virt_io_addr);
#endif
register_pci_controller(&au1x_controller);
return 0;
}
static __init void ja_pci1_init(void)
{
uint32_t mem0_base, mem0_size;
uint32_t io_base, io_size;
io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
/*
* Here we assume the I/O window of second bus to be contiguous with
* the first. A gap is no problem but would waste address space for
* remapping the port space.
*/
mv_pci_io_mem1_resource.start = mv_io_size;
mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
mv_pci_mem1_resource.start = mem0_base;
mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
mv_bus1_controller.pcic.mem_offset = mem0_base;
mv_bus1_controller.pcic.io_offset = 0;
ioport_resource.end = io_base + io_size -mv_io_base - 1;
register_pci_controller(&mv_bus1_controller.pcic);
mv_io_size = io_base + io_size - mv_io_base;
}
static __init int __init ocelot_g_pci_init(void)
{
unsigned long io_v_base;
if (gt_io_size) {
io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size);
if (!io_v_base)
panic("Could not ioremap I/O port range");
set_io_port_base(io_v_base);
}
register_pci_controller(>_bus0_controller.pcic);
register_pci_controller(>_bus1_controller.pcic);
return 0;
}
static int __init
ar2315_pci_init(void)
{
u32 reg;
if (ar231x_devtype != DEV_TYPE_AR2315)
return -ENODEV;
configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT, 1*1024*1024); /* Remap PCI config space */
ar231x_pci_controller.io_map_base =
(unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
msleep(10);
reg &= ~AR2315_RESET_PCIDMA;
ar231x_write_reg(AR2315_RESET, reg);
msleep(10);
ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
(AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
(AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
/* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
AR2315_PCIRST_LOW);
msleep(100);
/* Bring the PCI out of reset */
ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
0x1E | /* 1GB uncached */
(1 << 5) | /* Enable uncached */
(0x2 << 30) /* Base: 0x80000000 */
);
ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
msleep(500);
/* dirty hack - anyone with a datasheet that knows the memory map ? */
ioport_resource.start = 0x10000000;
ioport_resource.end = 0xffffffff;
iomem_resource.start = 0x10000000;
iomem_resource.end = 0xffffffff;
register_pci_controller(&ar231x_pci_controller);
return 0;
}
static int __init octeon_pci_setup(void)
{
int index;
octeon_pci_bar1_indexx_t bar1_index;
octeon_npi_mem_access_subid_t mem_access;
/* PCI I/O and PCI MEM values */
set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
ioport_resource.start = 0;
ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
if (!(octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST))
{
printk("Not in host mode, PCI Controller not initialized\n");
return 0;
}
octeon_pci_initialize();
mem_access.u64 = 0;
mem_access.s.esr = 1;
/**< Endian-Swap on read. */
mem_access.s.esw = 1;
/**< Endian-Swap on write. */
mem_access.s.nsr = 0;
/**< No-Snoop on read. */
mem_access.s.nsw = 0;
/**< No-Snoop on write. */
mem_access.s.ror = 0;
/**< Relax Read on read. */
mem_access.s.row = 0;
/**< Relax Order on write. */
mem_access.s.ba = OCTEON_PCI_MEMSPACE_BASE >> 36;
/**< PCI Address bits [63:36]. */
octeon_write_csr(OCTEON_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
/* place Octeon BAR 0 at zero, so pci scan remaps */
npi_write32(OCTEON_NPI_PCI_CFG04, 0);
npi_write32(OCTEON_NPI_PCI_CFG05, 0);
/* Remap the Octeon BAR 1 to map 0-128MB */
bar1_index.u32 = 0;
bar1_index.s.ca = 1; /* 1 = Put in L2 cache */
bar1_index.s.end_swp = 1; /* 1 = Byte swapping */
bar1_index.s.addr_v = 1; /* This entry is valid */
for (index = 0; index < 32; index++) {
bar1_index.s.addr_idx = index;
npi_write32(OCTEON_NPI_PCI_BAR1_INDEXX(index), bar1_index.u32);
}
npi_write32(OCTEON_NPI_PCI_CFG06, 0);
npi_write32(OCTEON_NPI_PCI_CFG07, 0);
/* place Octeon BAR 2 at zero, so pci scan remaps */
npi_write32(OCTEON_NPI_PCI_CFG08, 0);
npi_write32(OCTEON_NPI_PCI_CFG09, 0);
register_pci_controller(&octeon_pci_controller);
return 0;
}
static int __init pcibios_init(void)
{
setup_pcimap();
loongson_pci_controller.io_map_base = mips_io_port_base;
register_pci_controller(&loongson_pci_controller);
return 0;
}
static int __init bcm53000_pcibios_init(void)
{
ulong flags;
extern int pci_probe_only;
pci_probe_only = 1;
if (!(sih = si_kattach(SI_OSH)))
panic("sb_kattach failed");
spin_lock_init(&sih_lock);
spin_lock_irqsave(&sih_lock, flags);
hndpci_init(sih);
spin_unlock_irqrestore(&sih_lock, flags);
register_pci_controller(&bcm53000_controller_port0);
register_pci_controller(&bcm53000_controller_port1);
return 0;
}
static int __init pci_virtio_guest_setup(void)
{
pr_err("pci_virtio_guest_setup\n");
/* Virtio comes pre-assigned */
pci_set_flags(PCI_PROBE_ONLY);
pci_virtio_guest_controller.io_map_base = mips_io_port_base;
register_pci_controller(&pci_virtio_guest_controller);
return 0;
}
static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
{
u32 val;
if (WARN_ON(extpci_core))
return;
extpci_core = pc;
ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
/* Reset devices on the external PCI bus */
val = SSB_PCICORE_CTL_RST_OE;
val |= SSB_PCICORE_CTL_CLK_OE;
pcicore_write32(pc, SSB_PCICORE_CTL, val);
val |= SSB_PCICORE_CTL_CLK; /* Clock on */
pcicore_write32(pc, SSB_PCICORE_CTL, val);
udelay(150); /* Assertion time demanded by the PCI standard */
val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
pcicore_write32(pc, SSB_PCICORE_CTL, val);
val = SSB_PCICORE_ARBCTL_INTERN;
pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
udelay(1); /* Assertion time demanded by the PCI standard */
/*TODO cardbus mode */
/* 64MB I/O window */
pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
SSB_PCICORE_SBTOPCI_IO);
/* 64MB config space */
pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
SSB_PCICORE_SBTOPCI_CFG0);
/* 1GB memory window */
pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
/* Enable PCI bridge BAR0 prefetch and burst */
val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
/* Clear error conditions */
val = 0;
ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
/* Enable PCI interrupts */
pcicore_write32(pc, SSB_PCICORE_IMASK,
SSB_PCICORE_IMASK_INTA);
/* Ok, ready to run, register it to the system.
* The following needs change, if we want to port hostmode
* to non-MIPS platform. */
set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
/* Give some time to the PCI controller to configure itself with the new
* values. Not waiting at this point causes crashes of the machine. */
mdelay(10);
register_pci_controller(&ssb_pcicore_controller);
}
void __init sni_pcimt_init(void)
{
sni_pcimt_detect();
sni_pcimt_sc_init();
ioport_resource.end = sni_io_resource.end;
#ifdef CONFIG_PCI
PCIBIOS_MIN_IO = 0x9000;
register_pci_controller(&sni_controller);
#endif
sni_pcimt_resource_init();
}
void sni_pcimt_init(void)
{
sni_pcimt_resource_init();
sni_pcimt_detect();
sni_pcimt_sc_init();
rtc_mips_get_time = mc146818_get_cmos_time;
rtc_mips_set_time = mc146818_set_rtc_mmss;
board_time_init = sni_cpu_time_init;
#ifdef CONFIG_PCI
register_pci_controller(&sni_controller);
#endif
}
static int __init lasat_pci_setup(void)
{
printk(KERN_DEBUG "PCI: starting\n");
if (IS_LASAT_200())
lasat_pci_controller.pci_ops = &nile4_pci_ops;
else
lasat_pci_controller.pci_ops = >64xxx_pci0_ops;
register_pci_controller(&lasat_pci_controller);
return 0;
}
static int __init pcibios_init(void)
{
ict_pcimap();
loongson2e_pci_controller.io_map_base =
(unsigned long) ioremap(LOONGSON2E_IO_PORT_BASE,
loongson2e_pci_io_resource.end -
loongson2e_pci_io_resource.start + 1);
register_pci_controller(&loongson2e_pci_controller);
return 0;
}
static int __init gt64120_pci_init(void)
{
u32 tmp;
tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
tmp = GT_READ(GT_PCI0_BARE_OFS);
/* reset the whole PCI I/O space range */
ioport_resource.start = GT_PCI_IO_BASE;
ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
register_pci_controller(&hose_0);
return 0;
}
void __init plat_mem_setup(void)
{
static struct uart_port uart;
unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
int i;
_machine_restart = cobalt_machine_restart;
_machine_halt = cobalt_machine_halt;
pm_power_off = cobalt_machine_power_off;
set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
/* I/O port resource must include UART and LCD/buttons */
ioport_resource.end = 0x0fffffff;
/* request I/O space for devices used on all i[345]86 PCs */
for (i = 0; i < COBALT_IO_RESOURCES; i++)
request_resource(&ioport_resource, cobalt_io_resources + i);
/* Read the cobalt id register out of the PCI config space */
PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
printk("Cobalt board ID: %d\n", cobalt_board_id);
#ifdef CONFIG_PCI
register_pci_controller(&cobalt_pci_controller);
#endif
#ifdef CONFIG_SERIAL_8250
if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
#ifdef CONFIG_EARLY_PRINTK
cobalt_early_console();
#endif
uart.line = 0;
uart.type = PORT_UNKNOWN;
uart.uartclk = 18432000;
uart.irq = COBALT_SERIAL_IRQ;
uart.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
uart.iobase = 0xc800000;
uart.iotype = UPIO_PORT;
early_serial_setup(&uart);
}
#endif
}
static int pcibios_init(void)
{
#ifndef CONFIG_CPU_LOONGSON3
setup_pcimap(); //cww
#endif
loongson_pci_controller.io_map_base = mips_io_port_base;
loongson_pci_mem_resource.start = pci_mem_start_addr;
loongson_pci_mem_resource.end = pci_mem_end_addr;
register_pci_controller(&loongson_pci_controller);
return 0;
}
static void __init rbtx4939_pci_setup(void)
{
#ifdef CONFIG_PCI
int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
struct pci_controller *c = &txx9_primary_pcic;
register_pci_controller(c);
tx4939_report_pciclk();
tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
(__raw_readq(&tx4939_ccfgptr->pcfg) &
(TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
tx4939_report_pci1clk();
/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
register_pci_controller(c);
tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
}
tx4939_setup_pcierr_irq();
#endif /* CONFIG_PCI */
}
static int __init pcibios_init(void)
{
setup_pcimap();
loongson_pci_controller.io_map_base = mips_io_port_base;
#ifdef CONFIG_LEFI_FIRMWARE_INTERFACE
loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr;
loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;
#endif
register_pci_controller(&loongson_pci_controller);
#ifdef CONFIG_CPU_LOONGSON3
sbx00_acpi_init();
#endif
return 0;
}
static int __init bcm947xx_pcibios_init(void)
{
ulong flags;
extern int pci_probe_only;
pci_probe_only = 1;
if (!(sbh = sb_kattach()))
panic("sb_kattach failed");
spin_lock_init(&sbh_lock);
spin_lock_irqsave(&sbh_lock, flags);
sbpci_init(sbh);
spin_unlock_irqrestore(&sbh_lock, flags);
set_io_port_base((unsigned long)
ioremap_nocache(SB_PCI_MEM, 0x04000000));
register_pci_controller(&bcm947xx_controller);
return 0;
}
static int __init pmc_yosemite_setup(void)
{
unsigned long io_v_base;
io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
if (!io_v_base)
panic(ioremap_failed);
set_io_port_base(io_v_base);
TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
ioport_resource.end = TITAN_IO_SIZE - 1;
register_pci_controller(&py_controller);
return 0;
}
void __init plat_mem_setup(void)
{
static struct uart_port uart;
unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
int i;
_machine_restart = cobalt_machine_restart;
_machine_halt = cobalt_machine_halt;
pm_power_off = cobalt_machine_power_off;
set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
/* I/O port resource must include LCD/buttons */
ioport_resource.end = 0x0fffffff;
/* These resources have been reserved by VIA SuperI/O chip. */
for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
request_resource(&ioport_resource, cobalt_reserved_resources + i);
/* Read the cobalt id register out of the PCI config space */
PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
printk("Cobalt board ID: %d\n", cobalt_board_id);
#ifdef CONFIG_PCI
register_pci_controller(&cobalt_pci_controller);
#endif
if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
#ifdef CONFIG_SERIAL_8250
uart.line = 0;
uart.type = PORT_UNKNOWN;
uart.uartclk = 18432000;
uart.irq = COBALT_SERIAL_IRQ;
uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF |
UPF_SKIP_TEST;
uart.iotype = UPIO_MEM;
uart.mapbase = 0x1c800000;
early_serial_setup(&uart);
#endif
}
}
static void __init tx4927_pci_setup(void)
{
int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
struct pci_controller *c = &txx9_primary_pcic;
register_pci_controller(c);
if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
txx9_pci_option =
(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
TXX9_PCI_OPT_CLK_66; /* already configured */
/* Reset PCI Bus */
writeb(1, rbtx4927_pcireset_addr);
/* Reset PCIC */
txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
TXX9_PCI_OPT_CLK_66)
tx4927_pciclk66_setup();
mdelay(10);
/* clear PCIC reset */
txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
writeb(0, rbtx4927_pcireset_addr);
iob();
tx4927_report_pciclk();
tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
TXX9_PCI_OPT_CLK_AUTO &&
txx9_pci66_check(c, 0, 0)) {
/* Reset PCI Bus */
writeb(1, rbtx4927_pcireset_addr);
/* Reset PCIC */
txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
tx4927_pciclk66_setup();
mdelay(10);
/* clear PCIC reset */
txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
writeb(0, rbtx4927_pcireset_addr);
iob();
/* Reinitialize PCIC */
tx4927_report_pciclk();
tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
}
tx4927_setup_pcierr_irq();
}
static int __init gapspci_init(void)
{
char idbuf[16];
int i;
/*
* FIXME: All of this wants documenting to some degree,
* even some basic register definitions would be nice.
*
* I haven't seen anything this ugly since.. maple.
*/
for (i=0; i<16; i++)
idbuf[i] = inb(GAPSPCI_REGS+i);
if (strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
return -ENODEV;
outl(0x5a14a501, GAPSPCI_REGS+0x18);
for (i=0; i<1000000; i++)
cpu_relax();
if (inl(GAPSPCI_REGS+0x18) != 1)
return -EINVAL;
outl(0x01000000, GAPSPCI_REGS+0x20);
outl(0x01000000, GAPSPCI_REGS+0x24);
outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
outl(1, GAPSPCI_REGS+0x14);
outl(1, GAPSPCI_REGS+0x34);
/* Setting Broadband Adapter */
outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
return register_pci_controller(&dreamcast_pci_controller);
}
static int __init mace_init(void)
{
PCIBIOS_MIN_IO = 0x1000;
/* Clear any outstanding errors and enable interrupts */
mace->pci.error_addr = 0;
mace->pci.error = 0;
mace->pci.control = 0xff008500;
printk("MACE PCI rev %d\n", mace->pci.rev);
BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
"MACE PCI error", NULL));
ioport_resource.end = mace_pci_io_resource.end;
register_pci_controller(&mace_pci_controller);
return 0;
}
static int __init lasat_pci_setup(void)
{
printk("PCI: starting\n");
switch (mips_machtype) {
case MACH_LASAT_100:
lasat_pci_controller.pci_ops = >64xxx_pci0_ops;
break;
case MACH_LASAT_200:
lasat_pci_controller.pci_ops = &nile4_pci_ops;
break;
default:
panic("pcibios_init: mips_machtype incorrect");
}
register_pci_controller(&lasat_pci_controller);
return 0;
}
static int __init gapspci_init(void)
{
char idbuf[16];
int i;
for (i=0; i<16; i++)
idbuf[i] = inb(GAPSPCI_REGS+i);
if (strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
return -ENODEV;
outl(0x5a14a501, GAPSPCI_REGS+0x18);
for (i=0; i<1000000; i++)
cpu_relax();
if (inl(GAPSPCI_REGS+0x18) != 1)
return -EINVAL;
outl(0x01000000, GAPSPCI_REGS+0x20);
outl(0x01000000, GAPSPCI_REGS+0x24);
outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
outl(1, GAPSPCI_REGS+0x14);
outl(1, GAPSPCI_REGS+0x34);
/* Setting Broadband Adapter */
outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
return register_pci_controller(&dreamcast_pci_controller);
}
