static int start_ebs(bool is_start_paused) { int i; int ret; get_settings(); if (is_pmu_enabled()) { pmu_paused = is_start_paused; ret = register_hotcpu_notifier(&cpu_notifier_for_pmu); if (ret != 0) return ret; ret = allocate_pmu(); if (ret != 0) return ret; ret = register_pmu_isr(px_css_isr); if (ret != 0) return ret; for (i=0; i<COUNTER_A9_MAX_ID; i++) reg_value[i] = 0; on_each_cpu(start_pmu, &is_start_paused, 1); } return 0; }
static int start_pmu(bool is_start_paused) { int i; int ret; struct pmu_registers_pj4 pmu_regs; pmu_regs.pmnc = 0x0; pmu_regs.ccnt = 0x0; pmu_regs.cntens = 0x0; pmu_regs.cntenc = 0x0; pmu_regs.intens = 0x0; pmu_regs.intenc = 0x0; pmu_regs.flag = 0x0; for (i=0; i<PJ4_PMN_NUM; i++) { pmu_regs.evtsel[i] = 0; pmu_regs.pmncnt[i] = 0; } ret = allocate_pmu(); if (ret != 0) { return ret; } ret = register_pmu_isr(px_css_isr); if (ret != 0) { return ret; } /* disable PMU and clear CCNT & PMNx */ pmu_regs.pmnc = PJ4_Read_PMNC(); pmu_regs.pmnc &= ~0x1; //pmu_regs.pmnc |= 0x6; PJ4_Write_PMNC(pmu_regs.pmnc); for (i=0; i<g_ebs_settings.eventNumber; i++) { switch (g_ebs_settings.event[i].registerId) { case COUNTER_PJ4_PMU_CCNT: set_ccnt_events(&g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ4_PMU_PMN0: set_pmn_events(0, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ4_PMU_PMN1: set_pmn_events(1, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ4_PMU_PMN2: set_pmn_events(2, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ4_PMU_PMN3: set_pmn_events(3, &g_ebs_settings.event[i], &pmu_regs); break; default: break; } } /* disable all counters */ PJ4_Write_CNTENC(0xffffffff); /* disable all interrupts */ PJ4_Write_INTENC(0xffffffff); /* clear overflow flags */ PJ4_Write_FLAG(0xffffffff); /* write the counter values */ PJ4_WritePMUCounter(COUNTER_PJ4_PMU_CCNT, pmu_regs.ccnt); PJ4_WritePMUCounter(COUNTER_PJ4_PMU_PMN0, pmu_regs.pmncnt[0]); PJ4_WritePMUCounter(COUNTER_PJ4_PMU_PMN1, pmu_regs.pmncnt[1]); PJ4_WritePMUCounter(COUNTER_PJ4_PMU_PMN2, pmu_regs.pmncnt[2]); PJ4_WritePMUCounter(COUNTER_PJ4_PMU_PMN3, pmu_regs.pmncnt[3]); /* set events */ for (i=0; i<PJ4_PMN_NUM; i++) { PJ4_Write_PMNXSEL(i); PJ4_Write_PMNCNT(pmu_regs.pmncnt[i]); PJ4_Write_EVTSEL(pmu_regs.evtsel[i]); } if (is_start_paused) { pmu_regs.pmnc &= ~0x1; } else { pmu_regs.pmnc |= 0x1; } /* enable the interrupts */ PJ4_Write_INTENS(pmu_regs.intens); /* enable the counters */ PJ4_Write_CNTENS(pmu_regs.cntens); /* Enable PMU */ PJ4_Write_PMNC(pmu_regs.pmnc); return 0; }
static int start_pmu(bool is_start_paused) { int i; int ret; struct pmu_registers_pj1 pmu_regs; pmu_regs.inten = 0x0; pmu_regs.flag = 0x0; for (i=0; i<PJ1_PMN_NUM; i++) { pmu_regs.cor[i] = 0; pmu_regs.pmn[i] = 0; } /* There is no PMU interrupt in Avanta */ #if !defined(PX_SOC_AVANTA) ret = allocate_pmu(); if (ret != 0) { return ret; } ret = register_pmu_isr(px_css_isr); if (ret != 0) { return ret; } #endif for (i=0; i<g_ebs_settings.eventNumber; i++) { switch (g_ebs_settings.event[i].registerId) { case COUNTER_PJ1_PMU_PMN0: set_pmn_events(0, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ1_PMU_PMN1: set_pmn_events(1, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ1_PMU_PMN2: set_pmn_events(2, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ1_PMU_PMN3: set_pmn_events(3, &g_ebs_settings.event[i], &pmu_regs); break; default: break; } } /* disable all counters */ PJ1_WriteCOR(PJ1_PMU_COR0, 0); PJ1_WriteCOR(PJ1_PMU_COR1, 0); PJ1_WriteCOR(PJ1_PMU_COR2, 0); PJ1_WriteCOR(PJ1_PMU_COR3, 0); /* disable the interrupts */ PJ1_WriteINTEN(0x0); /* clear the overflow flags */ PJ1_WriteFLAG(0xf); /* write the counter values */ PJ1_WriteCounter(PJ1_PMU_PMN0, pmu_regs.pmn[0]); PJ1_WriteCounter(PJ1_PMU_PMN1, pmu_regs.pmn[1]); PJ1_WriteCounter(PJ1_PMU_PMN2, pmu_regs.pmn[2]); PJ1_WriteCounter(PJ1_PMU_PMN3, pmu_regs.pmn[3]); /* enable the interrupts */ PJ1_WriteINTEN(pmu_regs.inten); /* set events and enable the counters */ if (is_start_paused) { for (i=0; i<PJ1_PMN_NUM; i++) { pmu_regs.cor[i] &= ~0x1; } } else { for (i=0; i<PJ1_PMN_NUM; i++) { pmu_regs.cor[i] |= 0x1; } } PJ1_WriteCOR(PJ1_PMU_COR0, pmu_regs.cor[0]); PJ1_WriteCOR(PJ1_PMU_COR1, pmu_regs.cor[1]); PJ1_WriteCOR(PJ1_PMU_COR2, pmu_regs.cor[2]); PJ1_WriteCOR(PJ1_PMU_COR3, pmu_regs.cor[3]); return 0; }
static int start_pmu(bool is_start_paused) { int i; int ret; struct pmu_registers_pxa2 pmu_regs; pmu_regs.pmnc = 0x0; pmu_regs.inten = 0x0; pmu_regs.flag = 0x0; pmu_regs.ccnt = 0x0; for (i=0; i<PXA2_PMN_NUM; i++) pmu_regs.pmn[i] = 0; pmu_regs.evtsel = 0x0; ret = allocate_pmu(); if (ret != 0) { return ret; } ret = register_pmu_isr(px_css_isr); if (ret != 0) { return ret; } pmu_regs.pmnc = 0x10; WritePMUReg(PXA2_PMU_PMNC, pmu_regs.pmnc); for (i=0; i<g_ebs_settings.eventNumber; i++) { switch (g_ebs_settings.event[i].registerId) { case COUNTER_PXA2_PMU_CCNT: set_ccnt_events(&g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PXA2_PMU_PMN0: set_pmn_events(0, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PXA2_PMU_PMN1: set_pmn_events(1, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PXA2_PMU_PMN2: set_pmn_events(2, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PXA2_PMU_PMN3: set_pmn_events(3, &g_ebs_settings.event[i], &pmu_regs); break; default: break; } } if (!is_start_paused) { pmu_regs.pmnc &= 0x0f; pmu_regs.pmnc |= 0x1; } WritePMUReg(PXA2_PMU_CCNT, pmu_regs.ccnt); WritePMUReg(PXA2_PMU_PMN0, pmu_regs.pmn[0]); WritePMUReg(PXA2_PMU_PMN1, pmu_regs.pmn[1]); WritePMUReg(PXA2_PMU_PMN2, pmu_regs.pmn[2]); WritePMUReg(PXA2_PMU_PMN3, pmu_regs.pmn[3]); WritePMUReg(PXA2_PMU_EVTSEL, pmu_regs.evtsel); WritePMUReg(PXA2_PMU_FLAG, pmu_regs.flag); WritePMUReg(PXA2_PMU_INTEN, pmu_regs.inten); WritePMUReg(PXA2_PMU_PMNC, pmu_regs.pmnc); return 0; }