void write_ram_paging_port(void *device, uint8_t data) {
memory_mapping_state_t *state = device;
state->ram_bank_page = data & 0x7; // 0b111
log_message(state->asic->log, L_DEBUG, "memorymapping", "Set ram banking page to %d (at 0x%04X)", state->ram_bank_page, state->asic->cpu->registers.PC);
reload_mapping(state);
}
void init_mapping_ports(asic_t *asic) {
memory_mapping_state_t *state = malloc(sizeof(memory_mapping_state_t));
memset(state, 0, sizeof(memory_mapping_state_t));
state->asic = asic;
state->bank_a_flash = 1;
state->bank_b_flash = 1; // horrible, isn't it?
z80iodevice_t device_status_port = { state, read_device_status_port, write_device_status_port };
z80iodevice_t ram_paging_port = { state, read_ram_paging_port, write_ram_paging_port };
z80iodevice_t bank_a_paging_port = { state, read_bank_a_paging_port, write_bank_a_paging_port };
z80iodevice_t bank_b_paging_port = { state, read_bank_b_paging_port, write_bank_b_paging_port };
asic->cpu->devices[0x04] = device_status_port;
if (asic->device != TI83p) {
asic->cpu->devices[0x05] = ram_paging_port;
}
asic->cpu->devices[0x06] = bank_a_paging_port;
asic->cpu->devices[0x07] = bank_b_paging_port;
reload_mapping(state);
}
int test_memorymapping_others() {
asic_t *asic = asic_init(TI84p, NULL);
memory_mapping_state_t *state = asic->cpu->devices[0x04].device;
state->ram_bank_page = 1;
state->bank_a_page = 0;
state->bank_a_flash = 0;
reload_mapping(state);
ti_write_byte(asic->mmu, 0x4000, 0x12);
if (asic->mmu->ram[0] != 0x12) {
asic_free(asic);
return 1;
}
asic->mmu->ram[0x4000] = 0x34;
if (ti_read_byte(asic->mmu, 0xC000) != 0x34) {
asic_free(asic);
return 2;
}
state->map_mode = 1;
state->bank_a_page = 0;
state->bank_a_flash = 0;
state->bank_b_page = 0;
state->bank_b_flash = 0;
reload_mapping(state);
if (ti_read_byte(asic->mmu, 0x4000) != 0x12) {
asic_free(asic);
return 3;
}
if (ti_read_byte(asic->mmu, 0x8000) != 0x34) {
asic_free(asic);
return 4;
}
if (ti_read_byte(asic->mmu, 0xC000) != 0x12) {
asic_free(asic);
return 5;
}
return 0;
}
void write_device_status_port(void *device, uint8_t data) {
memory_mapping_state_t *state = device;
state->map_mode = data & 1;
log_message(state->asic->log, L_DEBUG, "memorymapping", "Set mapping mode to %d (at 0x%04X)", state->map_mode, state->asic->cpu->registers.PC);
reload_mapping(state);
write_timer_speed(state->asic->interrupts, data);
}
void write_bank_b_paging_port(void *device, uint8_t data) {
memory_mapping_state_t *state = device;
int is_flash = 0;
if (state->asic->device == TI83p) {
is_flash = (data & (1 << 6)) == 0;
data &= 0x1F; // 0b11111
} else {
is_flash = (data & (1 << 7)) == 0;
data &= 0x7F; // 0b111111
}
state->bank_b_flash = is_flash;
state->bank_b_page = data;
log_message(state->asic->log, L_DEBUG, "memorymapping", "Set bank B page to %c:%02X (at 0x%04X)", state->bank_b_flash ? 'F' : 'R', state->bank_b_page, state->asic->cpu->registers.PC);
reload_mapping(state);
}
