/** * @brief Interrupt handler for SMI# * * @param node * @param *state_save */ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { int i, dump = 0; u32 smi_sts; /* Update global variable pmbase */ pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc; /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ smi_sts = reset_smi_status(); /* Filter all non-enabled SMI events */ smi_sts = southbrigde_smi_mask_events(smi_sts); /* Call SMI sub handler for each of the status bits */ for (i = 0; i < 31; i++) { if (smi_sts & (1 << i)) { if (southbridge_smi[i]) southbridge_smi[i](node, state_save); else { printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " "handler available.\n", i); dump = 1; } } } if(dump) { dump_smi_status(smi_sts); } }
void southbridge_clear_smi_status(void) { /* Clear SMI status */ reset_smi_status(); /* Clear PM1 status */ reset_pm1_status(); /* Set EOS bit so other SMIs can occur. */ smi_set_eos(); }
static void smm_relocate(void) { u32 smi_en; printk(BIOS_DEBUG, "Initializing SMM handler..."); pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } /* copy the SMM relocation code */ memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); dump_tco_status(reset_tco_status()); /* Enable SMI generation: * - on TCO events * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) * No SMIs: * - on microcontroller writes (io 0x62/0x66) */ outl(smi_en | (TCO_EN | APMC_EN | SLP_SMI_EN | BIOS_EN | EOS | GBL_SMI_EN), pmbase + SMI_EN); /** * There are several methods of raising a controlled SMI# via * software, among them: * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * * Using the local apic is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so * I'm not too worried about the better of the methods at the moment */ /* raise an SMI interrupt */ printk(BIOS_SPEW, " ... raise SMI#\n"); outb(0x00, 0xb2); }
/** * @brief Interrupt handler for SMI# * @param node * @param state_save */ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { // FIXME: the necessary magic isn't available yet. the code // below is a partially adapted ICH7 version of the handler #if 0 u8 reg8; u16 pmctrl; u16 pm1_sts; u32 smi_sts, gpe0_sts, tco_sts; pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc; printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase); /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ smi_sts = reset_smi_status(); dump_smi_status(smi_sts); if (smi_sts & (1 << 21)) { // MONITOR global_nvs_t *gnvs = (global_nvs_t *)0xc00; u32 reg32; reg32 = RCBA32(0x1e00); TRSR - Trap Status Register //#if 0 /* Comment in for some useful debug */ for (i=0; i<4; i++) { if (reg32 & (1 << i)) { printk(BIOS_DEBUG, " io trap #%d\n", i); } } //#endif RCBA32(0x1e00) = reg32; TRSR reg32 = RCBA32(0x1e10); if ((reg32 & 0xfffc) != 0x808) { printk(BIOS_DEBUG, " trapped io address = 0x%x\n", reg32 & 0xfffc); printk(BIOS_DEBUG, " AHBE = %x\n", (reg32 >> 16) & 0xf); printk(BIOS_DEBUG, " read/write: %s\n", (reg32 & (1 << 24)) ? "read" : "write"); }
uint32_t clear_smi_status(void) { uint32_t sts = reset_smi_status(); /* * Check for power button status if nothing else is indicating an SMI * and SMIs aren't turned into SCIs. Apparently, there is no PM1 status * bit in the SMI status register. That makes things difficult for * determining if the power button caused an SMI. */ if (sts == 0 && !(inl(ACPI_PMIO_BASE + PM1_CNT) & SCI_EN)) { uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); /* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) sts |= (1 << FAKE_PM1_SMI_STS); } return print_smi_status(sts); }
static void smm_relocate(void) { u32 smi_en; u16 pm1_en; printk(BIOS_DEBUG, "Initializing SMM handler..."); pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); if (smi_en & GBL_SMI_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } /* copy the SMM relocation code */ memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); wbinvd(); printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); dump_alt_gp_smi_status(reset_alt_gp_smi_status()); dump_tco_status(reset_tco_status()); /* Enable SMI generation: * - on TCO events * - on APMC writes (io 0xb2) * - on writes to GBL_RLS (bios commands) * No SMIs: * - on microcontroller writes (io 0x62/0x66) */ smi_en = 0; /* reset SMI enables */ smi_en |= TCO_EN; smi_en |= APMC_EN; #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using * periodic SMIs. */ smi_en |= PERIODIC_EN; #endif smi_en |= BIOS_EN; /* The following need to be on for SMIs to happen */ smi_en |= EOS | GBL_SMI_EN; outl(smi_en, pmbase + SMI_EN); pm1_en = 0; pm1_en |= PWRBTN_EN; pm1_en |= GBL_EN; outw(pm1_en, pmbase + PM1_EN); /** * There are several methods of raising a controlled SMI# via * software, among them: * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * * Using the local apic is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so * I'm not too worried about the better of the methods at the moment */ /* raise an SMI interrupt */ printk(BIOS_SPEW, " ... raise SMI#\n"); outb(0x00, 0xb2); }
uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); }
void southbridge_smm_init(void) { u32 smi_en; u16 pm1_en; u32 gpe0_en; #if CONFIG_ELOG /* Log events from chipset before clearing */ pch_log_state(); #endif printk(BIOS_DEBUG, "Initializing southbridge SMI..."); pmbase = pci_read_config32(PCI_DEV(0, 0x1f, 0), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); dump_alt_gp_smi_status(reset_alt_gp_smi_status()); dump_tco_status(reset_tco_status()); /* Disable GPE0 PME_B0 */ gpe0_en = inl(pmbase + GPE0_EN); gpe0_en &= ~PME_B0_EN; outl(gpe0_en, pmbase + GPE0_EN); pm1_en = 0; pm1_en |= PWRBTN_EN; pm1_en |= GBL_EN; outw(pm1_en, pmbase + PM1_EN); /* Enable SMI generation: * - on TCO events * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) * No SMIs: * - on microcontroller writes (io 0x62/0x66) */ smi_en = 0; /* reset SMI enables */ #if 0 smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; #endif smi_en |= TCO_EN; smi_en |= APMC_EN; #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using * periodic SMIs. */ smi_en |= PERIODIC_EN; #endif smi_en |= SLP_SMI_EN; #if 0 smi_en |= BIOS_EN; #endif /* The following need to be on for SMIs to happen */ smi_en |= EOS | GBL_SMI_EN; outl(smi_en, pmbase + SMI_EN); }