static int idtcps_probe(struct rio_dev *rdev, const struct rio_device_id *id) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); spin_lock(&rdev->rswitch->lock); if (rdev->rswitch->ops) { spin_unlock(&rdev->rswitch->lock); return -EINVAL; } rdev->rswitch->ops = &idtcps_switch_ops; if (rdev->do_enum) { /* set TVAL = ~50us */ rio_write_config_32(rdev, rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, CPS_NO_ROUTE); } spin_unlock(&rdev->rswitch->lock); return 0; }
/* * idtg3_em_handler - device-specific error handler * * If the link is down (PORT_UNINIT) does nothing - this is considered * as link partner removal from the port. * * If the link is up (PORT_OK) - situation is handled as *new* device insertion. * In this case ERR_STOP bits are cleared by issuing soft reset command to the * reporting port. Inbound and outbound ackIDs are cleared by the reset as well. * This way the port is synchronized with freshly inserted device (assuming it * was reset/powered-up on insertion). * * TODO: This is not sufficient in a situation when a link between two devices * was down and up again (e.g. cable disconnect). For that situation full ackID * realignment process has to be implemented. */ static int idtg3_em_handler(struct rio_dev *rdev, u8 pnum) { u32 err_status; u32 rval; rio_read_config_32(rdev, RIO_DEV_PORT_N_ERR_STS_CSR(rdev, pnum), &err_status); /* Do nothing for device/link removal */ if (err_status & RIO_PORT_N_ERR_STS_PORT_UNINIT) return 0; /* When link is OK we have a device insertion. * Request port soft reset to clear errors if they present. * Inbound and outbound ackIDs will be 0 after reset. */ if (err_status & (RIO_PORT_N_ERR_STS_OUT_ES | RIO_PORT_N_ERR_STS_INP_ES)) { rio_read_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum), &rval); rio_write_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum), rval | RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST); udelay(10); rio_write_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum), rval); msleep(500); } return 0; }
static int idtg2_em_handler(struct rio_dev *rdev, UINT8 portnum) { UINT32 regval, em_perrdet, em_ltlerrdet; #ifdef DEBUG_SRIO char achBuffer[80]; #endif rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); if (em_ltlerrdet) { /* Service Logical/Transport Layer Error(s) */ if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { /* Implementation specific error reported */ rio_read_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, ®val); #ifdef DEBUG_SRIO sprintf(achBuffer,"RIO: %s Implementation Specific LTL errors" \ " 0x%x @(0x%x)\n", rio_name(rdev), em_ltlerrdet, regval); sysDebugWriteString(achBuffer); #endif /* Clear implementation specific address capture CSR */ rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); } } rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); if (em_perrdet) { /* Service Port-Level Error(s) */ if (em_perrdet & REM_PED_IMPL_SPEC) { /* Implementation Specific port error reported */ /* Get IS errors reported */ rio_read_config_32(rdev, IDT_PORT_ISERR_DET(portnum), ®val); #ifdef DEBUG_SRIO sprintf(achBuffer,"RIO: %s Implementation Specific Port" \ " errors 0x%x\n", rio_name(rdev), regval); sysDebugWriteString(achBuffer); #endif /* Clear all implementation specific events */ rio_write_config_32(rdev, IDT_PORT_ISERR_DET(portnum), 0); } } return 0; }
static int idtg2_probe(struct rio_dev *rdev, const struct rio_device_id *id) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); spin_lock(&rdev->rswitch->lock); if (rdev->rswitch->ops) { spin_unlock(&rdev->rswitch->lock); return -EINVAL; } rdev->rswitch->ops = &idtg2_switch_ops; if (rdev->do_enum) { /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE); } /* Create device-specific sysfs attributes */ idtg2_sysfs(rdev, true); spin_unlock(&rdev->rswitch->lock); return 0; }
static int idtg3_probe(struct rio_dev *rdev, const struct rio_device_id *id) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); spin_lock(&rdev->rswitch->lock); if (rdev->rswitch->ops) { spin_unlock(&rdev->rswitch->lock); return -EINVAL; } rdev->rswitch->ops = &idtg3_switch_ops; if (rdev->do_enum) { /* Disable hierarchical routing support: Existing fabric * enumeration/discovery process (see rio-scan.c) uses 8-bit * flat destination ID routing only. */ rio_write_config_32(rdev, 0x5000 + RIO_BC_RT_CTL_CSR, 0); } spin_unlock(&rdev->rswitch->lock); return 0; }
int idtg2_switch_init(struct rio_dev *rdev, int do_enum) { #ifdef DEBUG_SRIO char achBuffer[40]; sprintf(achBuffer,"RIO: %s for %s\n", __func__, rio_name(rdev)); sysDebugWriteString(achBuffer); #endif rdev->rswitch->add_entry = idtg2_route_add_entry; rdev->rswitch->get_entry = idtg2_route_get_entry; rdev->rswitch->clr_table = idtg2_route_clr_table; rdev->rswitch->set_domain = idtg2_set_domain; rdev->rswitch->get_domain = idtg2_get_domain; rdev->rswitch->em_init = idtg2_em_init; rdev->rswitch->em_handle = idtg2_em_handler; if (do_enum) { /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE); } return 0; }
static int idtg2_em_handler(struct rio_dev *rdev, u8 portnum) { u32 regval, em_perrdet, em_ltlerrdet; rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); if (em_ltlerrdet) { if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { rio_read_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, ®val); pr_debug("RIO: %s Implementation Specific LTL errors" \ " 0x%x @(0x%x)\n", rio_name(rdev), em_ltlerrdet, regval); rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); } } rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); if (em_perrdet) { if (em_perrdet & REM_PED_IMPL_SPEC) { rio_read_config_32(rdev, IDT_PORT_ISERR_DET(portnum), ®val); pr_debug("RIO: %s Implementation Specific Port" \ " errors 0x%x\n", rio_name(rdev), regval); rio_write_config_32(rdev, IDT_PORT_ISERR_DET(portnum), 0); } } return 0; }
/* * This routine performs device-specific initialization only. * All standard EM configuration should be performed at upper level. */ static int idtg3_em_init(struct rio_dev *rdev) { int i, tmp; u32 rval; pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); /* Disable assertion of interrupt signal */ rio_write_config_32(rdev, RIO_EM_DEV_INT_EN, 0); /* Disable port-write event notifications during initialization */ rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL, RIO_EM_PW_TX_CTRL_PW_DIS); /* Configure Port-Write notifications for hot-swap events */ tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo); for (i = 0; i < tmp; i++) { rio_read_config_32(rdev, RIO_DEV_PORT_N_ERR_STS_CSR(rdev, i), &rval); if (rval & RIO_PORT_N_ERR_STS_PORT_UA) continue; /* Clear events signaled before enabling notification */ rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(i), 0); /* Enable event notifications */ rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERRRATE_EN(i), RIO_EM_PN_ERRRATE_EN_OK2U | RIO_EM_PN_ERRRATE_EN_U2OK); /* Enable port-write generation on events */ rio_write_config_32(rdev, RIO_PLM_SPx_PW_EN(i), RIO_PLM_SPx_PW_EN_OK2U | RIO_PLM_SPx_PW_EN_LINIT); } /* Set Port-Write destination port */ tmp = RIO_GET_PORT_NUM(rdev->swpinfo); rio_write_config_32(rdev, RIO_PW_ROUTE, 1 << tmp); /* Enable sending port-write event notifications */ rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL, 0); /* set TVAL = ~50us */ rio_write_config_32(rdev, rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); return 0; }
static int idtcps_switch_init(struct rio_dev *rdev, int do_enum) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); rdev->rswitch->add_entry = idtcps_route_add_entry; rdev->rswitch->get_entry = idtcps_route_get_entry; rdev->rswitch->clr_table = idtcps_route_clr_table; rdev->rswitch->set_domain = idtcps_set_domain; rdev->rswitch->get_domain = idtcps_get_domain; rdev->rswitch->em_init = NULL; rdev->rswitch->em_handle = NULL; if (do_enum) { /* set TVAL = ~50us */ rio_write_config_32(rdev, rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, CPS_NO_ROUTE); } return 0; }
static int tsi568_em_init(struct rio_dev *rdev) { u32 regval; int portnum; pr_debug("TSI568 %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); for (portnum = 0; portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) { rio_read_config_32(rdev, TSI568_SP_MODE(portnum), ®val); rio_write_config_32(rdev, TSI568_SP_MODE(portnum), regval | TSI568_SP_MODE_PW_DIS); } return 0; }
static int idtg2_switch_init(struct rio_dev *rdev, int do_enum) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); rdev->rswitch->add_entry = idtg2_route_add_entry; rdev->rswitch->get_entry = idtg2_route_get_entry; rdev->rswitch->clr_table = idtg2_route_clr_table; rdev->rswitch->set_domain = idtg2_set_domain; rdev->rswitch->get_domain = idtg2_get_domain; rdev->rswitch->em_init = idtg2_em_init; rdev->rswitch->em_handle = idtg2_em_handler; rdev->rswitch->sw_sysfs = idtg2_sysfs; if (do_enum) { /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE); } return 0; }
static int idtg2_em_init(struct rio_dev *rdev) { u32 regval; int i, tmp; /* * This routine performs device-specific initialization only. * All standard EM configuration should be performed at upper level. */ pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); /* Set Port-Write info CSR: PRIO=3 and CRF=1 */ rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000); /* * Configure LT LAYER error reporting. */ /* Enable standard (RIO.p8) error reporting */ rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN, REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR | REM_LTL_ERR_UNSUPTR); /* Use Port-Writes for LT layer error reporting. * Enable per-port reset */ rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val); rio_write_config_32(rdev, IDT_DEV_CTRL_1, regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); /* * Configure PORT error reporting. */ /* Report all RIO.p8 errors supported by device */ rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037); /* Configure reporting of implementation specific errors/events */ rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC, IDT_PORT_INIT_TX_ACQUIRED); /* Use Port-Writes for port error reporting and enable error logging */ tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo); for (i = 0; i < tmp; i++) { rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val); rio_write_config_32(rdev, IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | IDT_PORT_OPS_PL_ELOG | IDT_PORT_OPS_LL_ELOG | IDT_PORT_OPS_LT_ELOG); } /* Overwrite error log if full */ rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR); /* * Configure LANE error reporting. */ /* Disable line error reporting */ rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0); /* Use Port-Writes for lane error reporting (when enabled) * (do per-lane update because lanes may have different configuration) */ tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16; for (i = 0; i < tmp; i++) { rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val); rio_write_config_32(rdev, IDT_LANE_CTRL(i), regval | IDT_LANE_CTRL_GENPW); } /* * Configure AUX error reporting. */ /* Disable JTAG and I2C Error capture */ rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0); /* Disable JTAG and I2C Error reporting/logging */ rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0); /* Disable Port-Write notification from JTAG */ rio_write_config_32(rdev, IDT_JTAG_CTRL, 0); /* Disable Port-Write notification from I2C */ rio_read_config_32(rdev, IDT_I2C_MCTRL, ®val); rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW); /* * Configure CFG_BLK error reporting. */ /* Disable Configuration Block error capture */ rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0); /* Disable Port-Writes for Configuration Block error reporting */ rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, ®val); rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT, regval & ~IDT_CFGBLK_ERR_REPORT_GENPW); /* set TVAL = ~50us */ rio_write_config_32(rdev, rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); return 0; }
static int idtg2_em_init(struct rio_dev *rdev) { u32 regval; int i, tmp; pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000); rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN, REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR | REM_LTL_ERR_UNSUPTR); rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val); rio_write_config_32(rdev, IDT_DEV_CTRL_1, regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037); rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC, IDT_PORT_INIT_TX_ACQUIRED); tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo); for (i = 0; i < tmp; i++) { rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val); rio_write_config_32(rdev, IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | IDT_PORT_OPS_PL_ELOG | IDT_PORT_OPS_LL_ELOG | IDT_PORT_OPS_LT_ELOG); } rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR); rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0); tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16; for (i = 0; i < tmp; i++) { rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val); rio_write_config_32(rdev, IDT_LANE_CTRL(i), regval | IDT_LANE_CTRL_GENPW); } rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0); rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0); rio_write_config_32(rdev, IDT_JTAG_CTRL, 0); rio_read_config_32(rdev, IDT_I2C_MCTRL, ®val); rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW); rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0); rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, ®val); rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT, regval & ~IDT_CFGBLK_ERR_REPORT_GENPW); rio_write_config_32(rdev, rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); return 0; }
static int cn6xxx_probe(struct rio_dev *dev, const struct rio_device_id *id) { u32 data; cvmx_sriomaintx_m2s_bar2_start_t sriomaintx_m2s_bar2_start; cvmx_sriomaintx_lcs_ba0_t sriomaintx_lcs_ba0; cvmx_sriomaintx_lcs_ba1_t sriomaintx_lcs_ba1; cvmx_sriomaintx_m2s_bar1_start0_t sriomaintx_m2s_bar1_start0; cvmx_sriomaintx_m2s_bar1_start1_t sriomaintx_m2s_bar1_start1; cvmx_sriomaintx_m2s_bar0_start0_t sriomaintx_m2s_bar0_start0; cvmx_sriomaintx_m2s_bar0_start1_t sriomaintx_m2s_bar0_start1; cvmx_sriomaintx_core_enables_t sriomaintx_core_enables; cvmx_sriomaintx_port_gen_ctl_t sriomaintx_port_gen_ctl; cvmx_sriomaintx_port_0_ctl_t sriomaintx_port_0_ctl; const char *state; int index; if (rio_read_config_32(dev, CVMX_SRIOMAINTX_IR_PI_PHY_STAT(0), &data)) return -1; switch (data & 0x3ff) { case 0x0: state = "Silent"; break; case 0x2: state = "Seek"; break; case 0x4: state = "Discovery"; break; case 0x8: state = "1x Mode Lane 0"; break; case 0x10: state = "1x Mode Lane 1"; break; case 0x20: state = "1x Mode Lane 2"; break; case 0x40: state = "1x Recovery"; break; case 0x80: state = "2x Mode"; break; case 0x100: state = "2x Recovery"; break; case 0x200: state = "4x Mode"; break; default: state = "Reserved"; break; } dev_info(&dev->dev, "Link state: %s\n", state); /* Setup BAR2 */ sriomaintx_m2s_bar2_start.u32 = 0; sriomaintx_m2s_bar2_start.s.addr64 = BAR2_ADDRESS >> 48; sriomaintx_m2s_bar2_start.s.addr48 = BAR2_ADDRESS >> 41; sriomaintx_m2s_bar2_start.s.esx = 0; sriomaintx_m2s_bar2_start.s.cax = 0; sriomaintx_m2s_bar2_start.s.addr66 = 0; // BAR2_ADDRESS >> 64; sriomaintx_m2s_bar2_start.s.enable = 1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR2_START(0), sriomaintx_m2s_bar2_start.u32)) return -1; dev_info(&dev->dev, "BAR2 0x%016llx - 0x%016llx\n", BAR2_ADDRESS, BAR2_ADDRESS + BAR2_SIZE - 1); /* Setup Maintinance */ sriomaintx_lcs_ba0.u32 = 0; sriomaintx_lcs_ba0.s.lcsba = MAINT_ADDRESS >> 35; sriomaintx_lcs_ba1.u32 = 0; sriomaintx_lcs_ba1.s.lcsba = (MAINT_ADDRESS >> 24) & 0x7ff; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_LCS_BA0(0), sriomaintx_lcs_ba0.u32)) return -1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_LCS_BA1(0), sriomaintx_lcs_ba1.u32)) return -1; dev_info(&dev->dev, "Maintenance 0x%016llx - 0x%016llx\n", MAINT_ADDRESS, MAINT_ADDRESS + MAINT_SIZE - 1); /* Setup BAR1 */ sriomaintx_m2s_bar1_start0.u32 = 0; sriomaintx_m2s_bar1_start0.s.addr64 = BAR1_ADDRESS >> 48; sriomaintx_m2s_bar1_start0.s.addr48 = BAR1_ADDRESS >> 32; sriomaintx_m2s_bar1_start1.u32 = 0; sriomaintx_m2s_bar1_start1.s.addr32 = (BAR1_ADDRESS >> 20) & 0xfff; sriomaintx_m2s_bar1_start1.s.barsize = BAR1_SHIFT; sriomaintx_m2s_bar1_start1.s.addr66 = 0; // BAR1_ADDRESS >> 64; sriomaintx_m2s_bar1_start1.s.enable = 1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR1_START0(0), sriomaintx_m2s_bar1_start0.u32)) return -1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR1_START1(0), sriomaintx_m2s_bar1_start1.u32)) return -1; dev_info(&dev->dev, "BAR1 0x%016llx - 0x%016llx\n", BAR1_ADDRESS, BAR1_ADDRESS + BAR1_SIZE - 1); /* Setup BAR0 */ sriomaintx_m2s_bar0_start0.u32 = 0; sriomaintx_m2s_bar0_start0.s.addr64 = BAR0_ADDRESS >> 48; sriomaintx_m2s_bar0_start0.s.addr48 = BAR0_ADDRESS >> 32; sriomaintx_m2s_bar0_start1.u32 = 0; sriomaintx_m2s_bar0_start1.s.addr32 = (BAR0_ADDRESS >> 14) & 0x3ffff; sriomaintx_m2s_bar0_start1.s.addr66 = 0; // BAR0_ADDRESS >> 64; sriomaintx_m2s_bar0_start1.s.enable = 1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR0_START0(0), sriomaintx_m2s_bar0_start0.u32)) return -1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR0_START1(0), sriomaintx_m2s_bar0_start1.u32)) return -1; dev_info(&dev->dev, "BAR0 0x%016llx - 0x%016llx\n", BAR0_ADDRESS, BAR0_ADDRESS + BAR0_SIZE - 1); /* Set enables */ sriomaintx_core_enables.u32 = 0; sriomaintx_core_enables.s.imsg1 = 1; sriomaintx_core_enables.s.imsg0 = 1; sriomaintx_core_enables.s.doorbell = 1; sriomaintx_core_enables.s.memory = 1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_CORE_ENABLES(0), sriomaintx_core_enables.u32)) return -1; /* Enable transaction mastering */ if (rio_read_config_32(dev, CVMX_SRIOMAINTX_PORT_GEN_CTL(0), &sriomaintx_port_gen_ctl.u32)) return -1; sriomaintx_port_gen_ctl.s.menable = 1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_PORT_GEN_CTL(0), sriomaintx_port_gen_ctl.u32)) return -1; /* Set link I/O enabled */ if (rio_read_config_32(dev, CVMX_SRIOMAINTX_PORT_0_CTL(0), &sriomaintx_port_0_ctl.u32)) return -1; sriomaintx_port_0_ctl.s.o_enable = 1; sriomaintx_port_0_ctl.s.i_enable = 1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_PORT_0_CTL(0), sriomaintx_port_0_ctl.u32)) return -1; if (rio_request_inb_dbell(dev->net->hport, dev, 0, 1, cn6xxx_doorbell)) { dev_err(&dev->dev, "Register for incomming doorbells failed\n"); return -1; } for (index=0; index<16; index++) { cvmx_sriomaintx_bar1_idxx_t sriomaintx_bar1_idxx; sriomaintx_bar1_idxx.u32 = 0; sriomaintx_bar1_idxx.s.la = index; sriomaintx_bar1_idxx.s.enable = 1; if (rio_write_config_32(dev, CVMX_SRIOMAINTX_BAR1_IDXX(index, 0), sriomaintx_bar1_idxx.u32)) return -1; } dev_info(&dev->dev, "SLI_MAC_CREDIT_CNT = 0x%llx\n", c6xxx_read_bar0(dev, CVMX_SLI_MAC_CREDIT_CNT)); if (rio_send_doorbell(dev, 0)) dev_err(&dev->dev, "Sending doorbell failed\n"); if (rio_send_doorbell(dev, 1)) dev_err(&dev->dev, "Sending doorbell failed\n"); return 0; }