static int veyron_init(void) { struct udevice *dev; struct clk clk; int ret; ret = regulator_get_by_platname("vdd_arm", &dev); if (ret) return ret; /* Slowly raise to max CPU voltage to prevent overshoot */ ret = regulator_set_value(dev, 1200000); if (ret) return ret; udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ ret = regulator_set_value(dev, 1400000); if (ret) return ret; udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ ret = rockchip_get_clk(&clk.dev); if (ret) return ret; clk.id = PLL_APLL; ret = clk_set_rate(&clk, 1800000000); if (IS_ERR_VALUE(ret)) return ret; return 0; }
int board_early_init_f(void) { const uintptr_t GRF_SOC_CON0 = 0xff770244; const uintptr_t GRF_SOC_CON2 = 0xff77024c; struct udevice *dev; int ret; /* * This init is done in SPL, but when chain-loading U-Boot SPL will * have been skipped. Allow the clock driver to check if it needs * setting up. */ ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return ret; } rk_setreg(GRF_SOC_CON2, 1 << 0); /* * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is * cleared */ rk_clrreg(GRF_SOC_CON0, 1 << 12); return 0; }
void *rockchip_get_cru(void) { struct rk3188_clk_priv *priv; struct udevice *dev; int ret; ret = rockchip_get_clk(&dev); if (ret) return ERR_PTR(ret); priv = dev_get_priv(dev); return priv->cru; }
static int veyron_init(void) { struct udevice *dev; struct clk clk; int ret; ret = regulator_get_by_platname("vdd_arm", &dev); if (ret) { debug("Cannot set regulator name\n"); return ret; } /* Slowly raise to max CPU voltage to prevent overshoot */ ret = regulator_set_value(dev, 1200000); if (ret) return ret; udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ ret = regulator_set_value(dev, 1400000); if (ret) return ret; udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ ret = rockchip_get_clk(&clk.dev); if (ret) return ret; clk.id = PLL_APLL; ret = clk_set_rate(&clk, 1800000000); if (IS_ERR_VALUE(ret)) return ret; ret = regulator_get_by_platname("vcc33_sd", &dev); if (ret) { debug("Cannot get regulator name\n"); return ret; } ret = regulator_set_value(dev, 3300000); if (ret) return ret; ret = regulators_enable_boot_on(false); if (ret) { debug("%s: Cannot enable boot on regulators\n", __func__); return ret; } return 0; }
void board_init_f(ulong dummy) { struct udevice *dev; int ret; /* Example code showing how to enable the debug UART on RK3288 */ /* Enable early UART on the RK3288 */ struct rk3288_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | GPIO7C6_MASK << GPIO7C6_SHIFT, GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); configure_l2ctlr(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } }
static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { static const struct { char *name; int id; } clks[] = { { "osc", CLK_OSC }, { "apll", CLK_ARM }, { "dpll", CLK_DDR }, { "cpll", CLK_CODEC }, { "gpll", CLK_GENERAL }, #ifdef CONFIG_ROCKCHIP_RK3036 { "mpll", CLK_NEW }, #else { "npll", CLK_NEW }, #endif }; int ret, i; struct udevice *dev; ret = rockchip_get_clk(&dev); if (ret) { printf("clk-uclass not found\n"); return 0; } for (i = 0; i < ARRAY_SIZE(clks); i++) { struct clk clk; ulong rate; clk.id = clks[i].id; ret = clk_request(dev, &clk); if (ret < 0) continue; rate = clk_get_rate(&clk); printf("%s: %lu\n", clks[i].name, rate); clk_free(&clk); } return 0; }
static int setup_arm_clock(void) { struct udevice *dev; struct clk clk; int ret; ret = rockchip_get_clk(&dev); if (ret) return ret; clk.id = CLK_ARM; ret = clk_request(dev, &clk); if (ret < 0) return ret; ret = clk_set_rate(&clk, 600000000); clk_free(&clk); return ret; }
void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; struct rk3188_pmu *pmu; int ret; /* Example code showing how to enable the debug UART on RK3188 */ #ifdef EARLY_UART #include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ #define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); printch('s'); printch('p'); printch('l'); printch('\n'); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } /* * Recover the bootrom's stackpointer. * For whatever reason needs to run after rockchip_get_clk. */ pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); if (IS_ERR(pmu)) error("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]); ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } setup_arm_clock(); #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif }
void board_init_f(ulong dummy) { struct udevice *pinctrl; struct udevice *dev; int ret; /* Example code showing how to enable the debug UART on RK3288 */ #include <asm/arch/grf_rk3288.h> /* Enable early UART on the RK3288 */ #define GRF_BASE 0xff770000 struct rk3288_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | GPIO7C6_MASK << GPIO7C6_SHIFT, GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); debug("\nspl:debug uart enabled in %s\n", __func__); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); configure_l2ctlr(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } #if !defined(CONFIG_SPL_OF_PLATDATA) if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { ret = phycore_init(); if (ret) { debug("Failed to set up phycore power settings: %d\n", ret); return; } } #endif #if !defined(CONFIG_SUPPORT_TPL) debug("\nspl:init dram\n"); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } #endif #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif }
void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; int ret; /* Example code showing how to enable the debug UART on RK3188 */ #ifdef EARLY_UART #include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ #define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); printch('s'); printch('p'); printch('l'); printch('\n'); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } setup_arm_clock(); #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif }