/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
struct chipset_power_state *ps;
int prev_sleep_state;
timestamp_add_now(TS_BEFORE_INITRAM);
ps = fill_power_state();
prev_sleep_state = chipset_prev_sleep_state(ps);
printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
if (prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
/* Initialize RAM */
raminit(params->mrc_params, prev_sleep_state);
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(prev_sleep_state == ACPI_S3);
}
static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
{
struct range_entry fsp_mem;
if (fsp_find_reserved_memory(&fsp_mem))
die("Failed to find FSP_RESERVED_MEMORY_RESOURCE_HOB!\n");
/* initialize cbmem by adding FSP reserved memory first thing */
if (!s3wake) {
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
range_entry_size(&fsp_mem));
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
range_entry_size(&fsp_mem))) {
if (CONFIG(HAVE_ACPI_RESUME)) {
printk(BIOS_ERR,
"Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
/* FIXME: A "system" reset is likely enough: */
full_reset();
}
}
/* make sure FSP memory is reserved in cbmem */
if (range_entry_base(&fsp_mem) !=
(uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY))
die("Failed to accommodate FSP reserved memory request!\n");
save_memory_training_data(s3wake, fsp_version);
/* Create romstage handof information */
romstage_handoff_init(s3wake);
}
asmlinkage void *post_cache_as_ram(void)
{
uint32_t family = amd_fam1x_cpu_family();
int s3resume = 0;
/* Verify that the BSP didn't overrun the lower stack
* boundary during romstage execution
*/
volatile uint32_t *lower_stack_boundary;
lower_stack_boundary =
(void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
- CONFIG_DCACHE_BSP_STACK_SIZE);
if ((*lower_stack_boundary) != 0xdeadbeef)
printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n");
s3resume = acpi_is_wakeup_s3();
prepare_romstage_ramstack(s3resume);
romstage_handoff_init(s3resume);
/* from here don't store more data in CAR */
if (family >= 0x1f && family <= 0x3f) {
/* Family 10h and 12h, 11h until shown otherwise */
vErrata343();
}
size_t car_size = car_data_size();
void *migrated_car = (void *)(CONFIG_RAMTOP - car_size);
print_car_debug("Copying data from cache to RAM...");
memcpy_(migrated_car, _car_relocatable_data_start, car_size);
print_car_debug(" Done\n");
print_car_debug("Verifying data integrity in RAM...");
if (memcmp_(migrated_car, _car_relocatable_data_start, car_size) == 0)
print_car_debug(" Done\n");
else
print_car_debug(" FAILED\n");
/* New stack grows right below migrated_car. */
print_car_debug("Switching to use RAM as stack...");
return migrated_car;
}
/* Platform has no romstage entry point under mainboard directory,
* so this one is named with prefix mainboard.
*/
void mainboard_romstage_entry(unsigned long bist)
{
sysinfo_t sysinfo;
int s3resume = 0;
int cbmem_initted;
u16 reg16;
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();
if (bist == 0)
enable_lapic();
/* First, run everything needed for console output. */
i82801ix_early_init();
setup_pch_gpios(&mainboard_gpio_map);
mb_setup_lpc();
mb_setup_superio();
console_init();
report_bist_failure(bist);
reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
gm45_early_reset();
}
/* ASPM related setting, set early by original BIOS. */
DMIBAR16(0x204) &= ~(3 << 10);
/* Check for S3 resume. */
s3resume = southbridge_detect_s3_resume();
/* RAM initialization */
enter_raminit_or_reset();
memset(&sysinfo, 0, sizeof(sysinfo));
get_mb_spd_addrmap(sysinfo.spd_map);
const struct device *dev;
dev = pcidev_on_root(2, 0);
if (dev)
sysinfo.enable_igd = dev->enabled;
dev = pcidev_on_root(1, 0);
if (dev)
sysinfo.enable_peg = dev->enabled;
get_gmch_info(&sysinfo);
mb_pre_raminit_setup(&sysinfo);
raminit(&sysinfo, s3resume);
mb_post_raminit_setup();
const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
/* Disable D4F0 (unknown signal controller). */
pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
init_pm(&sysinfo, 0);
i82801ix_dmi_setup();
gm45_late_init(sysinfo.stepping);
i82801ix_dmi_poll_vc1();
MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
init_iommu();
cbmem_initted = !cbmem_recovery(s3resume);
romstage_handoff_init(cbmem_initted && s3resume);
printk(BIOS_SPEW, "exit main()\n");
}
void romstage_common(const struct romstage_params *params)
{
int boot_mode;
int wake_from_s3;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (params->bist == 0)
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
haswell_early_initialization(HASWELL_MOBILE);
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
wake_from_s3 = 0;
#endif
}
/* There are hard coded assumptions of 2 meaning s3 wake. Normalize
* the users of the 2 literal here based off wake_from_s3. */
boot_mode = wake_from_s3 ? 2 : 0;
/* Prepare USB controller early in S3 resume */
if (wake_from_s3)
enable_usb_bar();
post_code(0x3a);
params->pei_data->boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
report_platform_info();
if (params->copy_spd != NULL)
params->copy_spd(params->pei_data);
sdram_initialize(params->pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3b);
intel_early_me_status();
quick_ram_check();
post_code(0x3e);
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
romstage_handoff_init(wake_from_s3);
post_code(0x3f);
if (IS_ENABLED(CONFIG_LPC_TPM))
init_tpm(wake_from_s3);
}
