static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev) { if (rt2x00_is_soc(rt2x00dev)) { rt2800_disable_radio(rt2x00dev); rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0); rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0); } }
/* * Device state switch handlers. */ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev, enum dev_state state) { int mask = (state == STATE_RADIO_IRQ_ON); u32 reg; unsigned long flags; /* * When interrupts are being enabled, the interrupt registers * should clear the register to assure a clean state. */ if (state == STATE_RADIO_IRQ_ON) { rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); /* * Enable tasklets. The beacon related tasklets are * enabled when the beacon queue is started. */ tasklet_enable(&rt2x00dev->txstatus_tasklet); tasklet_enable(&rt2x00dev->rxdone_tasklet); tasklet_enable(&rt2x00dev->autowake_tasklet); } spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®); rt2x00_set_field32(®, INT_MASK_CSR_RXDELAYINT, 0); rt2x00_set_field32(®, INT_MASK_CSR_TXDELAYINT, 0); rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, mask); rt2x00_set_field32(®, INT_MASK_CSR_AC0_DMA_DONE, 0); rt2x00_set_field32(®, INT_MASK_CSR_AC1_DMA_DONE, 0); rt2x00_set_field32(®, INT_MASK_CSR_AC2_DMA_DONE, 0); rt2x00_set_field32(®, INT_MASK_CSR_AC3_DMA_DONE, 0); rt2x00_set_field32(®, INT_MASK_CSR_HCCA_DMA_DONE, 0); rt2x00_set_field32(®, INT_MASK_CSR_MGMT_DMA_DONE, 0); rt2x00_set_field32(®, INT_MASK_CSR_MCU_COMMAND, 0); rt2x00_set_field32(®, INT_MASK_CSR_RXTX_COHERENT, 0); rt2x00_set_field32(®, INT_MASK_CSR_TBTT, mask); rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, mask); rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, mask); rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, mask); rt2x00_set_field32(®, INT_MASK_CSR_GPTIMER, 0); rt2x00_set_field32(®, INT_MASK_CSR_RX_COHERENT, 0); rt2x00_set_field32(®, INT_MASK_CSR_TX_COHERENT, 0); rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); if (state == STATE_RADIO_IRQ_OFF) { /* * Ensure that all tasklets are finished before * disabling the interrupts. */ tasklet_disable(&rt2x00dev->txstatus_tasklet); tasklet_disable(&rt2x00dev->rxdone_tasklet); tasklet_disable(&rt2x00dev->autowake_tasklet); } }
static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance) { struct rt2x00_dev *rt2x00dev = dev_instance; u32 reg, mask; /* Read status and ACK all interrupts */ rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); if (!reg) return IRQ_NONE; if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) return IRQ_HANDLED; /* * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits * for interrupts and interrupt masks we can just use the value of * INT_SOURCE_CSR to create the interrupt mask. */ mask = ~reg; if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) { rt2800pci_txstatus_interrupt(rt2x00dev); /* * Never disable the TX_FIFO_STATUS interrupt. */ rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1); } if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT)) tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet); if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT)) tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE)) tasklet_schedule(&rt2x00dev->rxdone_tasklet); if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) tasklet_schedule(&rt2x00dev->autowake_tasklet); /* * Disable all interrupts for which a tasklet was scheduled right now, * the tasklet will reenable the appropriate interrupts. */ spin_lock(&rt2x00dev->irqmask_lock); rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®); reg &= mask; rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); spin_unlock(&rt2x00dev->irqmask_lock); return IRQ_HANDLED; }
static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp) { int preamble_mask; u32 reg; /* * When short preamble is enabled, we should set bit 0x08 */ preamble_mask = erp->short_preamble << 3; rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, erp->ack_timeout); rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, erp->ack_consume_time); rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); rt2x00pci_register_read(rt2x00dev, ARCSR2, ®); rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10)); rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); rt2x00pci_register_read(rt2x00dev, ARCSR3, ®); rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20)); rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); rt2x00pci_register_read(rt2x00dev, ARCSR4, ®); rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55)); rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); rt2x00pci_register_read(rt2x00dev, ARCSR5, ®); rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110)); rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); rt2x00pci_register_read(rt2x00dev, CSR11, ®); rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); rt2x00pci_register_write(rt2x00dev, CSR11, reg); rt2x00pci_register_read(rt2x00dev, CSR18, ®); rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); rt2x00pci_register_write(rt2x00dev, CSR18, reg); rt2x00pci_register_read(rt2x00dev, CSR19, ®); rt2x00_set_field32(®, CSR19_DIFS, erp->difs); rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); rt2x00pci_register_write(rt2x00dev, CSR19, reg); }
static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev, const enum data_queue_qid qid) { u32 reg; if (qid == QID_BEACON) { rt2x00pci_register_write(rt2x00dev, CSR14, 0); } else { rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); rt2x00_set_field32(®, TXCSR0_ABORT, 1); rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); } }
static void rt2400pci_kill_tx_queue(struct data_queue *queue) { struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; u32 reg; if (queue->qid == QID_BEACON) { rt2x00pci_register_write(rt2x00dev, CSR14, 0); } else { rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); rt2x00_set_field32(®, TXCSR0_ABORT, 1); rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); } }
static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) { if (state == STATE_AWAKE) { rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02); rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP); } else if (state == STATE_SLEEP) { rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 0xffffffff); rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, 0xffffffff); rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01); } return 0; }
/* * TX data initialization */ static void rt2400pci_write_beacon(struct queue_entry *entry) { struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; struct queue_entry_priv_pci *entry_priv = entry->priv_data; struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); u32 word; u32 reg; /* * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ rt2x00pci_register_read(rt2x00dev, CSR14, ®); rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); rt2x00_set_field32(®, CSR14_TBCN, 0); rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); rt2x00pci_register_write(rt2x00dev, CSR14, reg); /* * Replace rt2x00lib allocated descriptor with the * pointer to the _real_ hardware descriptor. * After that, map the beacon to DMA and update the * descriptor. */ memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len); skbdesc->desc = entry_priv->desc; rt2x00queue_map_txskb(rt2x00dev, entry->skb); rt2x00_desc_read(entry_priv->desc, 1, &word); rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); rt2x00_desc_write(entry_priv->desc, 1, word); }
static void rt2800pci_clear_entry(struct queue_entry *entry) { struct queue_entry_priv_pci *entry_priv = entry->priv_data; struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; u32 word; if (entry->queue->qid == QID_RX) { rt2x00_desc_read(entry_priv->desc, 0, &word); rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma); rt2x00_desc_write(entry_priv->desc, 0, word); rt2x00_desc_read(entry_priv->desc, 1, &word); rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0); rt2x00_desc_write(entry_priv->desc, 1, word); /* * Set RX IDX in register to inform hardware that we have * handled this entry and it is available for reuse again. */ rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx); } else { rt2x00_desc_read(entry_priv->desc, 1, &word); rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1); rt2x00_desc_write(entry_priv->desc, 1, word); } }
static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev, const unsigned int word, const u8 value) { u32 reg; /* * Wait until the BBP becomes ready. */ reg = rt2400pci_bbp_check(rt2x00dev); if (rt2x00_get_field32(reg, BBPCSR_BUSY)) { ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n"); return; } /* * Write the data into the BBP. */ reg = 0; rt2x00_set_field32(®, BBPCSR_VALUE, value); rt2x00_set_field32(®, BBPCSR_REGNUM, word); rt2x00_set_field32(®, BBPCSR_BUSY, 1); rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); }
static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev, const unsigned int word, const u32 value) { u32 reg; unsigned int i; if (!word) return; for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt2x00pci_register_read(rt2x00dev, RFCSR, ®); if (!rt2x00_get_field32(reg, RFCSR_BUSY)) goto rf_write; udelay(REGISTER_BUSY_DELAY); } ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n"); return; rf_write: reg = 0; rt2x00_set_field32(®, RFCSR_VALUE, value); rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); rt2x00_set_field32(®, RFCSR_BUSY, 1); rt2x00pci_register_write(rt2x00dev, RFCSR, reg); rt2x00_rf_write(rt2x00dev, word, value); }
static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) { struct rt2x00_dev *rt2x00dev = dev_instance; u32 reg; /* * Get the interrupt sources & saved to local variable. * Write register value back to clear pending interrupts. */ rt2x00pci_register_read(rt2x00dev, CSR7, ®); rt2x00pci_register_write(rt2x00dev, CSR7, reg); if (!reg) return IRQ_NONE; if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) return IRQ_HANDLED; /* Store irqvalues for use in the interrupt thread. */ rt2x00dev->irqvalue[0] = reg; /* Disable interrupts, will be enabled again in the interrupt thread. */ rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF_ISR); return IRQ_WAKE_THREAD; }
/* * Configuration handlers. */ static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev, const unsigned int filter_flags) { u32 reg; /* * Start configuration steps. * Note that the version error will always be dropped * since there is no filter for it at this time. */ rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); rt2x00_set_field32(®, RXCSR0_DROP_CRC, !(filter_flags & FIF_FCSFAIL)); rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, !(filter_flags & FIF_PLCPFAIL)); rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, !(filter_flags & FIF_CONTROL)); rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, !(filter_flags & FIF_PROMISC_IN_BSS)); rt2x00_set_field32(®, RXCSR0_DROP_TODS, !(filter_flags & FIF_PROMISC_IN_BSS) && !rt2x00dev->intf_ap_count); rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); }
static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word, u8 *value) { u32 reg; mutex_lock(&rt2x00dev->csr_mutex); /* * Wait until the BBP becomes available, afterwards we * can safely write the read request into the register. * After the data has been written, we wait until hardware * returns the correct value, if at any time the register * doesn't become available in time, reg will be 0xffffffff * which means we return 0xff to the caller. */ if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg = 0; rt2x00_set_field32(®, BBPCSR_REGNUM, word); rt2x00_set_field32(®, BBPCSR_BUSY, 1); rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); WAIT_FOR_BBP(rt2x00dev, ®); } *value = rt2x00_get_field32(reg, BBPCSR_VALUE); mutex_unlock(&rt2x00dev->csr_mutex); }
static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) { u32 reg; unsigned int i; char put_to_sleep; char bbp_state; char rf_state; put_to_sleep = (state != STATE_AWAKE); rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®); rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); /* * Device is not guaranteed to be in the requested state yet. * We must wait until the register indicates that the * device has entered the correct state. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®); bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE); rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE); if (bbp_state == state && rf_state == state) return 0; msleep(10); } return -EBUSY; }
static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev) { /* * Disable power */ rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0); }
static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_conf *libconf) { u32 reg; rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); rt2x00pci_register_read(rt2x00dev, CSR12, ®); rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, libconf->conf->beacon_int * 16); rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, libconf->conf->beacon_int * 16); rt2x00pci_register_write(rt2x00dev, CSR12, reg); }
static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev) { u32 reg; rt2x00pci_register_read(rt2x00dev, LEDCSR, ®); rt2x00_set_field32(®, LEDCSR_LINK, 0); rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0); rt2x00pci_register_write(rt2x00dev, LEDCSR, reg); }
static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev) { u32 reg; /* * Initialize rings. */ rt2400pci_init_rxring(rt2x00dev); rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0); rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1); rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON); rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON); /* * Initialize registers. */ rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size); rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit); rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].stats.limit); rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit); rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma); rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma); rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, rt2x00dev->bcn[1].data_dma); rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, rt2x00dev->bcn[0].data_dma); rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit); rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, rt2x00dev->rx->data_dma); rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); return 0; }
static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) { struct rt2x00_dev *rt2x00dev = dev_instance; u32 reg; /* * Get the interrupt sources & saved to local variable. * Write register value back to clear pending interrupts. */ rt2x00pci_register_read(rt2x00dev, CSR7, ®); rt2x00pci_register_write(rt2x00dev, CSR7, reg); if (!reg) return IRQ_NONE; if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) return IRQ_HANDLED; /* * Handle interrupts, walk through all bits * and run the tasks, the bits are checked in order of * priority. */ /* * 1 - Beacon timer expired interrupt. */ if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) rt2x00lib_beacondone(rt2x00dev); /* * 2 - Rx ring done interrupt. */ if (rt2x00_get_field32(reg, CSR7_RXDONE)) rt2x00pci_rxdone(rt2x00dev); /* * 3 - Atim ring transmit done interrupt. */ if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) rt2400pci_txdone(rt2x00dev, QID_ATIM); /* * 4 - Priority ring transmit done interrupt. */ if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) rt2400pci_txdone(rt2x00dev, QID_AC_BE); /* * 5 - Tx ring transmit done interrupt. */ if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) rt2400pci_txdone(rt2x00dev, QID_AC_BK); return IRQ_HANDLED; }
static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, struct ieee80211_tx_queue_params *params) { u32 reg; rt2x00pci_register_read(rt2x00dev, CSR11, ®); rt2x00_set_field32(®, CSR11_CWMIN, params->cw_min); rt2x00_set_field32(®, CSR11_CWMAX, params->cw_max); rt2x00pci_register_write(rt2x00dev, CSR11, reg); }
static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, const int cw_min, const int cw_max) { u32 reg; rt2x00pci_register_read(rt2x00dev, CSR11, ®); rt2x00_set_field32(®, CSR11_CWMIN, cw_min); rt2x00_set_field32(®, CSR11_CWMAX, cw_max); rt2x00pci_register_write(rt2x00dev, CSR11, reg); }
static void rt2400pci_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) { struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; u32 reg; rt2x00pci_register_read(rt2x00dev, CSR14, ®); rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); rt2x00pci_register_write(rt2x00dev, CSR14, reg); rt2x00queue_map_txskb(entry); rt2400pci_write_tx_desc(entry, txdesc); rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); rt2x00pci_register_write(rt2x00dev, CSR14, reg); }
static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) { struct rt2x00_dev *rt2x00dev = dev_instance; u32 reg, mask; rt2x00pci_register_read(rt2x00dev, CSR7, ®); rt2x00pci_register_write(rt2x00dev, CSR7, reg); if (!reg) return IRQ_NONE; if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) return IRQ_HANDLED; mask = reg; if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); if (rt2x00_get_field32(reg, CSR7_RXDONE)) tasklet_schedule(&rt2x00dev->rxdone_tasklet); if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { tasklet_schedule(&rt2x00dev->txstatus_tasklet); rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); } spin_lock(&rt2x00dev->irqmask_lock); rt2x00pci_register_read(rt2x00dev, CSR8, ®); reg |= mask; rt2x00pci_register_write(rt2x00dev, CSR8, reg); spin_unlock(&rt2x00dev->irqmask_lock); return IRQ_HANDLED; }
/* * Device state switch handlers. */ static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev, enum dev_state state) { u32 reg; rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); rt2x00_set_field32(®, RXCSR0_DISABLE_RX, state == STATE_RADIO_RX_OFF); rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); }
static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp) { int preamble_mask; u32 reg; /* * When short preamble is enabled, we should set bit 0x08 */ preamble_mask = erp->short_preamble << 3; rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, erp->ack_timeout); rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, erp->ack_consume_time); rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); rt2x00pci_register_read(rt2x00dev, ARCSR2, ®); rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10)); rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); rt2x00pci_register_read(rt2x00dev, ARCSR3, ®); rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20)); rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); rt2x00pci_register_read(rt2x00dev, ARCSR4, ®); rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55)); rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); rt2x00pci_register_read(rt2x00dev, ARCSR5, ®); rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110)); rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); }
static void rt2400pci_kick_tx_queue(struct data_queue *queue) { struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; u32 reg; rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue->qid == QID_AC_BE)); rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue->qid == QID_AC_BK)); rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue->qid == QID_ATIM)); rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); }
static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_conf *libconf) { u32 reg; rt2x00pci_register_read(rt2x00dev, CSR11, ®); rt2x00_set_field32(®, CSR11_LONG_RETRY, libconf->conf->long_frame_max_tx_count); rt2x00_set_field32(®, CSR11_SHORT_RETRY, libconf->conf->short_frame_max_tx_count); rt2x00pci_register_write(rt2x00dev, CSR11, reg); }
static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, struct ieee80211_tx_control *control) { struct rt2x00_dev *rt2x00dev = hw->priv; struct rt2x00_intf *intf = vif_to_intf(control->vif); struct queue_entry_priv_pci_tx *priv_tx; struct skb_frame_desc *skbdesc; u32 reg; if (unlikely(!intf->beacon)) return -ENOBUFS; priv_tx = intf->beacon->priv_data; /* * Fill in skb descriptor */ skbdesc = get_skb_frame_desc(skb); memset(skbdesc, 0, sizeof(*skbdesc)); skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED; skbdesc->data = skb->data; skbdesc->data_len = skb->len; skbdesc->desc = priv_tx->desc; skbdesc->desc_len = intf->beacon->queue->desc_size; skbdesc->entry = intf->beacon; /* * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ rt2x00pci_register_read(rt2x00dev, CSR14, ®); rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); rt2x00_set_field32(®, CSR14_TBCN, 0); rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); rt2x00pci_register_write(rt2x00dev, CSR14, reg); /* * mac80211 doesn't provide the control->queue variable * for beacons. Set our own queue identification so * it can be used during descriptor initialization. */ control->queue = RT2X00_BCN_QUEUE_BEACON; rt2x00lib_write_tx_desc(rt2x00dev, skb, control); /* * Enable beacon generation. * Write entire beacon with descriptor to register, * and kick the beacon generator. */ memcpy(priv_tx->data, skb->data, skb->len); rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue); return 0; }
static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, const enum data_queue_qid queue) { u32 reg; if (queue == QID_BEACON) { rt2x00pci_register_read(rt2x00dev, CSR14, ®); if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) { rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); rt2x00_set_field32(®, CSR14_TBCN, 1); rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); rt2x00pci_register_write(rt2x00dev, CSR14, reg); } return; } rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE)); rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK)); rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM)); rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); }