ErrorStatus fnSetAlarmClock(uint8_t h,uint8_t m,uint8_t setting)
{
uint8_t t;
if ((h>=24)||(m>=60))
return ERROR;
rt_kprintf("\n===Enter Alarm Clock Mode===\n");
/* Set Alarm Time */
t = IIC_Read(DS3231_ADDRESS,DS3231_CONTROL) & 0xFC;
if (setting)
{
IIC_Write(DS3231_ADDRESS,DS3231_CONTROL,t | 0x01);
IIC_Write(DS3231_ADDRESS,DS3231_A1_S,0x00);
IIC_Write(DS3231_ADDRESS,DS3231_A1_M,(m%10)|((m/10)<<4));
IIC_Write(DS3231_ADDRESS,DS3231_A1_H,(h%10)|((h/10)<<4));
IIC_Write(DS3231_ADDRESS,DS3231_A1_D,0x80);
}else{
IIC_Write(DS3231_ADDRESS,DS3231_CONTROL,t | 0x02);
IIC_Write(DS3231_ADDRESS,DS3231_A2_M,(m%10)|((m/10)<<4));
IIC_Write(DS3231_ADDRESS,DS3231_A2_H,(h%10)|((h/10)<<4));
IIC_Write(DS3231_ADDRESS,DS3231_A2_D,0x80);
}
/* Clear Alarm Flag */
t = IIC_Read(DS3231_ADDRESS,DS3231_CON_STA);
t &= 0xFC;
IIC_Write(DS3231_ADDRESS,DS3231_CON_STA,t);
rt_event_send(en_event,EVENT_TEMP_CLOCK);
rt_thread_delay_hmsm(0,0,1,0);
rt_event_send(reg_event,REG_ALARM_MSK);
reg_output[REG_ALARM] = REG_Convert(REG_HexToReg(m%10),REG_HexToReg(m/10),REG_HexToReg(h%10),REG_HexToReg(h/10),1,0);
rt_thread_delay_hmsm(0,0,1,0);
reg_output[REG_ALARM] = 0xFFFFFFFF;
rt_thread_delay_hmsm(0,0,0,62);
reg_output[REG_ALARM] = 0xFFFFFFFE;
rt_thread_delay_hmsm(0,0,0,62);
reg_output[REG_ALARM] = 0xFFFFFEBF;
rt_thread_delay_hmsm(0,0,0,62);
reg_output[REG_ALARM] = 0xFFFEBFF7;
rt_thread_delay_hmsm(0,0,0,62);
reg_output[REG_ALARM] = 0xFEBFF7FF;
rt_thread_delay_hmsm(0,0,0,62);
reg_output[REG_ALARM] = 0xBFF7FFFF;
rt_thread_delay_hmsm(0,0,0,62);
reg_output[REG_ALARM] = 0xF7FFFFFF;
rt_thread_delay_hmsm(0,0,0,62);
reg_output[REG_ALARM] = 0xFFFFFFFF;
rt_thread_delay_hmsm(0,0,0,62);
StandBy();
return SUCCESS;
}
/* netconn callback function */
void rx_callback(struct netconn *conn, enum netconn_evt evt, rt_uint16_t len)
{
if (evt == NETCONN_EVT_RCVPLUS)
{
rt_event_send(telnet->nw_event, NW_RX);
}
if (conn->state == NETCONN_CLOSE)
{
rt_event_send(telnet->nw_event, NW_CLOSED);
}
}
void cc1101_isr()
{
if(GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_4) ==Bit_SET)
{
rt_event_send(&cc1101_event,GDO0_H);
//DEBUG("GDO0_H in int \r\n");
}
else
{
rt_event_send(&cc1101_event,GDO0_L);
// DEBUG("GDO0_L in int \r\n");
}
}
static rt_err_t uart485_tl16_8_rx_ind(rt_device_t dev, rt_size_t size)
{
rt_event_send(&em_protocol_data_event_set, EVENT_BIT_TL16_8_RECV_DATA);
++rx_ind_cnt[7];
return RT_EOK;
}
static rt_err_t uart485_3_rx_ind(rt_device_t dev, rt_size_t size)
{
// rt_sem_release(&uart485_3_rx_byte_sem);
rt_event_send(&em_protocol_data_event_set, EVENT_BIT_UART485_3_RECV_DATA);
u485_ind_debug(("%s(), size:%d\n", __func__, size));
return RT_EOK;
}
void fnAlarm(void)
{
rt_uint32_t e;
uint8_t buf,int_m,t=0;
uint16_t delay1,delay2,strength;
rt_thread_delay_hmsm(0,0,3,0);
int_m = (clock_m+5)%60;
rt_kprintf("It is %d:%d now\nAlarm Level %d\n",clock_h,clock_m,t);
rt_event_send(reg_event,REG_ALARM_MSK);
while (rt_mq_recv(key_mq,&buf,sizeof(uint8_t),0)!=RT_EOK)
{
if (clock_m==int_m)
{
t+=1;
int_m = (int_m+5)%60;
rt_kprintf("Alarm Level %d\n",t);
}
switch (t)
{
case 0: delay1 = 500; delay2 = 4500; strength = 400; break;
case 1: delay1 = 1000; delay2 = 2000; strength = 600; break;
case 2: delay1 = 500; delay2 = 500; strength = 800; break;
default: delay1 = 500; delay2 = 250; strength = 1000; break;
}
SetAlarm(strength);
rt_thread_delay_hmsm(0,0,0,delay1);
SetAlarm(0);
Animate(delay2);
}
rt_event_recv(reg_event,REG_ALARM_MSK,RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR,0,&e);
return;
}
void vMBPortSerialEnable(BOOL xRxEnable, BOOL xTxEnable)
{
rt_uint32_t recved_event;
if (xRxEnable)
{
/* enable RX interrupt */
serial->ops->control(serial, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_RX);
/* switch 485 to receive mode */
rt_pin_write(MODBUS_SLAVE_RT_CONTROL_PIN_INDEX, PIN_HIGH);//PIN_LOW);
}
else
{
/* switch 485 to transmit mode */
rt_pin_write(MODBUS_SLAVE_RT_CONTROL_PIN_INDEX, PIN_LOW);//PIN_HIGH);
/* disable RX interrupt */
serial->ops->control(serial, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_FLAG_INT_RX);
}
if (xTxEnable)
{
/* start serial transmit */
rt_event_send(&event_serial, EVENT_SERIAL_TRANS_START);
}
else
{
/* stop serial transmit */
rt_event_recv(&event_serial, EVENT_SERIAL_TRANS_START,
RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, 0,
&recved_event);
}
}
void sonar_thread_entry(void* parameter)
{
rt_kprintf("start sonar\n");
while(1)
{
GPIO_SetBits(GPIOE,GPIO_Pin_7);
rt_thread_delay(RT_TICK_PER_SECOND*10/1000);
GPIO_ResetBits(GPIOE,GPIO_Pin_7);
rt_thread_delay(RT_TICK_PER_SECOND*50/1000);
sonar_h=Moving_Median(PWM8_Time/58.0f*ahrs.g_z,sonar_avr,SAMPLE_COUNT);
ahrs.height_v=HV_A*(ahrs.height_v+ahrs.height_acc*0.06f)+(1.0f-HV_A)*((sonar_h-ahrs.height)/0.06f);
ahrs.height=sonar_h;
h=(u16)sonar_h;
sonar_state=sonar_h>3.0f&&sonar_h<150.0f;
ahrs_state.sonar=!sonar_state;
rt_event_send(&ahrs_event,AHRS_EVENT_SONAR);
}
}
void
jffs2_stop_garbage_collect_thread(struct jffs2_sb_info *c)
{
struct super_block *sb=OFNI_BS_2SFFJ(c);
cyg_mtab_entry *mte;
rt_uint32_t e;
//RT_ASSERT(sb->s_gc_thread_handle);
D1(printk("jffs2_stop_garbage_collect_thread\n"));
/* Stop the thread and wait for it if necessary */
rt_event_send(&sb->s_gc_thread_flags,GC_THREAD_FLAG_STOP);
D1(printk("jffs2_stop_garbage_collect_thread wait\n"));
rt_event_recv(&sb->s_gc_thread_flags,
GC_THREAD_FLAG_HAS_EXIT,
RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
RT_WAITING_FOREVER, &e);
// Kill and free the resources ... this is safe due to the flag
// from the thread.
rt_thread_detach(&sb->s_gc_thread);
rt_sem_detach(&sb->s_lock);
rt_event_detach(&sb->s_gc_thread_flags);
}
void jffs2_garbage_collect_trigger(struct jffs2_sb_info *c)
{
struct super_block *sb=OFNI_BS_2SFFJ(c);
/* Wake up the thread */
D1(printk("jffs2_garbage_collect_trigger\n"));
rt_event_send(&sb->s_gc_thread_flags,GC_THREAD_FLAG_TRIG);
}
/**
* This is modbus master request process success callback function.
* @note There functions will block modbus master poll while execute OS waiting.
* So,for real-time of system.Do not execute too much waiting process.
*
*/
void vMBMasterCBRequestScuuess( void ) {
/**
* @note This code is use OS's event mechanism for modbus master protocol stack.
* If you don't use OS, you can change it.
*/
rt_event_send(&xMasterOsEvent, EV_MASTER_PROCESS_SUCESS);
/* You can add your code under here. */
}
/**
* This is modbus master execute function error process callback function.
* @note There functions will block modbus master poll while execute OS waiting.
* So,for real-time of system.Do not execute too much waiting process.
*
* @param ucDestAddress destination salve address
* @param pucPDUData PDU buffer data
* @param ucPDULength PDU buffer length
*
*/
void vMBMasterErrorCBExecuteFunction(UCHAR ucDestAddress, const UCHAR* pucPDUData,
USHORT ucPDULength) {
/**
* @note This code is use OS's event mechanism for modbus master protocol stack.
* If you don't use OS, you can change it.
*/
rt_event_send(&xMasterOsEvent, EV_MASTER_ERROR_EXECUTE_FUNCTION);
/* You can add your code under here. */
}
/**
* This is modbus master receive data error process callback function.
* @note There functions will block modbus master poll while execute OS waiting.
* So,for real-time of system.Do not execute too much waiting process.
*
* @param ucDestAddress destination salve address
* @param pucPDUData PDU buffer data
* @param ucPDULength PDU buffer length
*
*/
void vMBMasterErrorCBReceiveData(UCHAR ucDestAddress, const UCHAR* pucPDUData,
USHORT ucPDULength) {
/**
* @note This code is use OS's event mechanism for modbus master protocol stack.
* If you don't use OS, you can change it.
*/
rt_event_send(&xMasterOsEvent, EV_MASTER_ERROR_RECEIVE_DATA);
/* You can add your code under here. */
}
void EXTI1_IRQHandler(void)
{
if(EXTI_GetITStatus(EXTI_Line1)!= RESET )
{
//ProcessInt0();
EXTI_ClearFlag(EXTI_Line1);
EXTI_ClearITPendingBit(EXTI_Line1);
rt_event_send(&event,(1 << 0));
}
}
/* send telnet option to remote */
static void telnet_send_option(struct telnet_session* telnet, rt_uint8_t option, rt_uint8_t value)
{
rt_uint8_t optbuf[4];
optbuf[0] = TELNET_IAC;
optbuf[1] = option;
optbuf[2] = value;
optbuf[3] = 0;
rt_sem_take(telnet->tx_ringbuffer_lock, RT_WAITING_FOREVER);
rb_put(&telnet->tx_ringbuffer, optbuf, 3);
rt_sem_release(telnet->tx_ringbuffer_lock);
/* trigger a tx event */
rt_event_send(telnet->nw_event, NW_TX);
}
void ENET_IRQHandler(void)
{
rt_uint32_t status;
/* enter interrupt */
rt_interrupt_enter();
status = LPC_EMAC->IntStatus;
if (status & INT_RX_DONE)
{
/* Disable EMAC RxDone interrupts. */
LPC_EMAC->IntEnable = INT_TX_DONE;
/* a frame has been received */
eth_device_ready(&(lpc17xx_emac_device.parent));
}
else if (status & INT_TX_DONE)
{
/* set event */
rt_event_send(&tx_event, 0x01);
}
if (status & INT_RX_OVERRUN)
{
rt_kprintf("rx overrun\n");
}
if (status & INT_TX_UNDERRUN)
{
rt_kprintf("tx underrun\n");
}
if (status & INT_SOFT_INT){
rt_kprintf("!!!!!!!!!!!!!!eth soft int\n");
}
if(status & INT_WAKEUP){
rt_kprintf("!!!!!!!!!!!!!1eth wakeup\n");
}
/* Clear the interrupt. */
LPC_EMAC->IntClear = status;
/* leave interrupt */
rt_interrupt_leave();
}
void DMA1_Stream0_IRQHandler(void) //I2C1 RX
{
rt_interrupt_enter();
if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TCIF0))
{
I2C_TRACE("RXTC\n");
/* clear DMA flag */
DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TCIF0 );
DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, DISABLE);
DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE);
if( i2cStatus == S6 )
{
i2cStatus = S_STOP;
I2C1->CR1 |= CR1_STOP_Set;
rt_event_send(&i2c_event, I2C_COMPLETE);
}
}
if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_HTIF0))
{
I2C_TRACE("RXHT\n");
DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_HTIF0 );
}
if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TEIF0))
{
I2C_TRACE("RXTE\n");
DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TEIF0 );
}
if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_FEIF0))
{
I2C_TRACE("RXFE\n");
DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_FEIF0 );
}
if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_DMEIF0))
{
I2C_TRACE("RXDME\n");
DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_DMEIF0 );
}
rt_interrupt_leave();
}
u8 get_dmp()
{
dmp_read_fifo(gyro, accel, quat, &sensor_timestamp, &sensors, &more);
if (sensors & INV_WXYZ_QUAT)
{
q0 = (float)quat[0] / q30;
q1 = (float)quat[1] / q30;
q2 = (float)quat[2] / q30;
q3 = (float)quat[3] / q30;
mpu_gryo_pitch = MoveAve_WMA(gyro[0], MPU6050_GYR_FIFO[0], 8);
mpu_gryo_roll = MoveAve_WMA(gyro[1], MPU6050_GYR_FIFO[1], 8);
mpu_gryo_yaw = MoveAve_WMA(gyro[2], MPU6050_GYR_FIFO[2], 8);
ahrs.gryo_pitch = -mpu_gryo_pitch * gyroscale / 32767.0f;
ahrs.gryo_roll = -mpu_gryo_roll * gyroscale / 32767.0f;
ahrs.gryo_yaw = -mpu_gryo_yaw * gyroscale / 32767.0f;
ahrs.degree_roll = -asin(-2 * q1 * q3 + 2 * q0* q2)* 57.3f + settings.angle_diff_roll; //+ Pitch_error; // pitch
ahrs.degree_pitch = -atan2(2 * q2 * q3 + 2 * q0 * q1, -2 * q1 * q1 - 2 * q2* q2 + 1)* 57.3f + settings.angle_diff_pitch; //+ Roll_error; // roll
if (!has_hmc5883)
ahrs.degree_yaw = atan2(2 * (q1*q2 + q0*q3), q0*q0 + q1*q1 - q2*q2 - q3*q3) * 57.3f; //+ Yaw_error;
ahrs.time_span = Timer4_GetSec();
if (en_out_ahrs)
rt_kprintf("%d,%d,%d %d\n",
(s32)(ahrs.degree_pitch),
(s32)(ahrs.degree_roll),
(s32)(ahrs.degree_yaw),
(u32)(1.0f / ahrs.time_span));
rt_event_send(&ahrs_event, AHRS_EVENT_Update);
dmp_retry = 0;
return 1;
}
lost:
dmp_retry++;
return 0;
}
static void
jffs2_garbage_collect_thread(unsigned long data)
{
struct jffs2_sb_info *c=(struct jffs2_sb_info *)data;
struct super_block *sb=OFNI_BS_2SFFJ(c);
cyg_mtab_entry *mte;
rt_uint32_t flag = 0;
D1(printk("jffs2_garbage_collect_thread START\n"));
while(1) {
rt_event_recv(&sb->s_gc_thread_flags,
GC_THREAD_FLAG_TRIG | GC_THREAD_FLAG_STOP,
RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
cyg_current_time() + CYGNUM_JFFS2_GS_THREAD_TICKS,
&flag);
if (flag & GC_THREAD_FLAG_STOP)
break;
D1(printk("jffs2: GC THREAD GC BEGIN\n"));
mte=(cyg_dir *) sb->s_root;
RT_ASSERT(mte != NULL);
// rt_mutex_take(&mte->fs->syncmode, RT_WAITING_FOREVER);
if (jffs2_garbage_collect_pass(c) == -ENOSPC) {
printf("No space for garbage collection. "
"Aborting JFFS2 GC thread\n");
break;
}
// rt_mutex_release(&mte->fs->syncmode);
D1(printk("jffs2: GC THREAD GC END\n"));
}
D1(printk("jffs2_garbage_collect_thread EXIT\n"));
rt_event_send(&sb->s_gc_thread_flags,GC_THREAD_FLAG_HAS_EXIT);
}
static rt_size_t telnet_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
const rt_uint8_t *ptr;
ptr = (rt_uint8_t*)buffer;
rt_sem_take(telnet->tx_ringbuffer_lock, RT_WAITING_FOREVER);
while (size)
{
if (*ptr == '\n')
rb_putchar(&telnet->tx_ringbuffer, '\r');
if (rb_putchar(&telnet->tx_ringbuffer, *ptr) == 0) /* overflow */
break;
ptr ++; size --;
}
rt_sem_release(telnet->tx_ringbuffer_lock);
/* send to network side */
rt_event_send(telnet->nw_event, NW_TX);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
/*
Only 1 byte READ using Interrupt or Polling otherwise using DMA
*/
void I2C1_EV_IRQHandler()
{
__IO uint16_t regSR1, regSR2;
__IO uint32_t regSR;
int i=10;
rt_interrupt_enter();
//rt_hw_led_on(10);
regSR1 = I2C1->SR1;
regSR2 = I2C1->SR2;
regSR = (regSR2 << 16) | regSR1;
//rt_kprintf("EV=> SR1: 0x%x\tSR2: 0x%x\tSR: 0x%x status: %d\n", regSR1, regSR2, regSR, i2cStatus);
if( (regSR & I2C_EVENT_MASTER_MODE_SELECT) == I2C_EVENT_MASTER_MODE_SELECT) //EV5
{
if( i2cStatus == S1 ) //Send TX Command
{
I2C1->DR = DevAddr & 0xFE;
i2cStatus = S2;
}
else if( i2cStatus == S4 ) //Send RX Command
{
I2C1->DR = DevAddr | 0x01;
i2cStatus = S5;
}
regSR1 = 0;
regSR2 = 0;
}
if( (regSR & I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)== I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ) //EV6
{
switch( i2cStatus )
{
case S2: //Send 1st memory address phase
{
//I2C_DMACmd(I2C1, ENABLE);
I2C1->DR = MemAddr[0];
if( memtype == I2C_MEM_1Byte )
i2cStatus = S2_2;
else if( memtype == I2C_MEM_2Bytes )
i2cStatus = S2_1;
}
break;
case S5: //Set RX buffer phase
{
if( i2cFlag == I2C_READ_DMA )
{
I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_RX);
I2C1->CR2 |= CR2_LAST_Set | CR2_DMAEN_Set;
DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);
}
else if( i2cFlag == I2C_READ_INTERRUPT )
{
I2C1->CR2 |= I2C_IT_BUF;
I2C1->CR1 &= CR1_ACK_Reset;
/* Program the STOP */
I2C1->CR1 |= CR1_STOP_Set;
}
i2cStatus = S6;
}
break;
}
regSR1 = 0;
regSR2 = 0;
//dump_i2c_register(I2C1);
}
if((regSR & I2C_EVENT_MASTER_BYTE_RECEIVED) == I2C_EVENT_MASTER_BYTE_RECEIVED) //EV7
{
//Interrupt RX complete phase
if( i2cStatus == S6 && i2cFlag == I2C_READ_INTERRUPT )
{
*i2c_buf = I2C1->DR;
i2cStatus = S_STOP;
rt_event_send(&i2c_event, I2C_COMPLETE);
}
}
if( (regSR & I2C_EVENT_MASTER_BYTE_TRANSMITTED) == I2C_EVENT_MASTER_BYTE_TRANSMITTED ) //EV8_2
{
//Start TX/RX phase
if(i2cStatus == S3)
{
DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 );
DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
switch (i2cFlag)
{
case I2C_WRITE:
i2cStatus = S_STOP;
I2C1->CR1 |= CR1_STOP_Set;
rt_event_send(&i2c_event, I2C_COMPLETE);
break;
case I2C_READ_DMA:
i2cStatus = S4;
I2C1->CR1 |= CR1_START_Set;
break;
case I2C_READ_POLLING:
i2cStatus = S_STOP;
rt_event_send(&i2c_event, I2C_COMPLETE);
I2C1->CR2 &= ~(CR2_LAST_Set | I2C_IT_EVT | CR2_DMAEN_Set);
I2C1->CR1 |= CR1_START_Set;
break;
case I2C_READ_INTERRUPT:
i2cStatus = S4;
I2C1->CR1 |= CR1_START_Set;
break;
}
}
if( i2cStatus == S2_1 ) //Send 2nd memory address
{
if( memtype == I2C_MEM_2Bytes ) //memory address has 2 bytes
{
I2C1->DR = MemAddr[1];
i2cStatus = S2_2;
}
if( i2cFlag == I2C_READ_POLLING || i2cFlag == I2C_READ_DMA || i2cFlag == I2C_READ_INTERRUPT)
{
i2cStatus = S3;
}
}
if( i2cStatus == S2_2 ) //Set TX DAM phase
{
I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_TX);
I2C1->CR2 |= CR2_DMAEN_Set;
i2cStatus = S3;
}
}
rt_interrupt_leave();
}
static rt_err_t data_rx_callback(rt_device_t dev, rt_size_t size)
{
rt_event_send(cmd.recv_event,0x01);
return RT_EOK;
}
void SetLed(uint8_t x)
{
extern rt_event_t f_led;
rt_event_send(f_led,(1<<(x-1)));
}
/*数据到达回调函数,发送事件到gprs_send_data_package*/
rt_err_t uart_input(rt_device_t dev, rt_size_t size)
{
rt_event_send(&rev_event, REV_DATA);
return RT_EOK;
}
rt_inline void stm32_i2c_send_ev(struct stm32_i2c_bus *bus, rt_uint32_t ev)
{
rt_event_send(&bus->ev, 0x01 << ev);
}
void rt_thread_alarm_entry (void *parameter)
{
uint8_t buf;
uint16_t t;
rt_uint32_t e;
AlarmerInit();
SetAlarm(0);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
if (PWR_GetFlagStatus(PWR_FLAG_WU)==SET)
{
rt_kprintf("\n\nWaken up by DS3231\n");
if ((IIC_Read(DS3231_ADDRESS, DS3231_CON_STA)) & 0x01) fnAlarm();
IIC_Write(DS3231_ADDRESS, DS3231_CON_STA,0x80);
}
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, DISABLE);
while (rt_mq_recv(key_mq,&buf,sizeof(uint8_t),10)==RT_EOK);
while (1)
{
do
{
rt_mq_recv(key_mq,&buf,sizeof(uint8_t),RT_WAITING_FOREVER);
}while(buf!=0);
t = 0;
reg_output[REG_ALARM]=0xF777F7F7;
rt_event_send(reg_event,REG_ALARM_MSK);
rt_mq_recv(key_mq,&buf,sizeof(uint8_t),RT_WAITING_FOREVER);
if (buf>9)
{
rt_event_recv(reg_event,REG_ALARM_MSK,RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR,0,&e);
continue;
}
t = buf;
reg_output[REG_ALARM]=(0x01000000*REG_HexToReg(buf)) | (0x00FFFFFF & reg_output[REG_ALARM]) | 0x80000000;
rt_mq_recv(key_mq,&buf,sizeof(uint8_t),RT_WAITING_FOREVER);
if (buf>9)
{
rt_event_recv(reg_event,REG_ALARM_MSK,RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR,0,&e);
continue;
}
t = t*10+buf;
reg_output[REG_ALARM]=(0x00010000*REG_HexToReg(buf)) | (0xFF00FFFF & reg_output[REG_ALARM]);
rt_mq_recv(key_mq,&buf,sizeof(uint8_t),RT_WAITING_FOREVER);
if (buf>9)
{
rt_event_recv(reg_event,REG_ALARM_MSK,RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR,0,&e);
continue;
}
t = t*10+buf;
reg_output[REG_ALARM]=(0x00000100*REG_HexToReg(buf)) | (0xFFFF00FF & reg_output[REG_ALARM]);
rt_mq_recv(key_mq,&buf,sizeof(uint8_t),RT_WAITING_FOREVER);
if (buf>9)
{
rt_event_recv(reg_event,REG_ALARM_MSK,RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR,0,&e);
continue;
}
t = t*10+buf;
reg_output[REG_ALARM]=(0x00000001*REG_HexToReg(buf)) | (0xFFFFFF00 & reg_output[REG_ALARM]);
rt_mq_recv(key_mq,&buf,sizeof(uint8_t),RT_WAITING_FOREVER);
if (buf<=9)
{
rt_event_recv(reg_event,REG_ALARM_MSK,RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR,0,&e);
continue;
}else
{
if (fnSetAlarmClock(t/100,t%100,buf==0x0B)==ERROR)
rt_event_recv(reg_event,REG_ALARM_MSK,RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR,0,&e);
}
}
}
void stopwatch(void)
{
rt_event_send(&rev_event, REV_STOPWATCH);
}
/**
* @brief This function handles the command response
*
* @param priv A pointer to wlan_private structure
* @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
*/
int wlan_process_rx_command(WlanCard *cardinfo)
{
WlanCard *card = cardinfo;
u16 RespCmd;
HostCmd_DS_COMMAND *resp;
int ret = WLAN_STATUS_SUCCESS;
u16 Result;
if (!card->CurCmd)
{
resp = (HostCmd_DS_COMMAND *) card->CmdResBuf;
WlanDebug(WlanErr, "CMD_RESP: NULL CurCmd, 0x%x\n", resp->Command);
ret = WLAN_STATUS_FAILURE;
goto done;
}
resp = (HostCmd_DS_COMMAND *) card->CmdResBuf;
RespCmd = resp->Command;
Result = resp->Result;
WlanDebug(WlanCmd, "CMD_RESP: 0x%x, result %d, len %d, seqno %d\n",RespCmd, Result, resp->Size, resp->SeqNum);
if (!(RespCmd & 0x8000))
{
WlanDebug(WlanErr,"CMD_RESP: Invalid response to command!");
card->CurCmdRetCode = WLAN_STATUS_FAILURE;
ret = WLAN_STATUS_FAILURE;
rt_event_send(&(card->cmdwaitevent), CmdWaitQWoken);
goto done;
}
/* Store the response code to CurCmdRetCode. */
card->CurCmdRetCode = resp->Result;
/* If the command is not successful, cleanup and return failure */
if ((Result != HostCmd_RESULT_OK || !(RespCmd & 0x8000)))
{
WlanDebug(WlanErr,"CMD_RESP: cmd %#x error, result=%#x\n",resp->Command, resp->Result);
/*
* Handling errors here
*/
switch (RespCmd)
{
case HostCmd_RET_HW_SPEC_INFO:
WlanDebug(WlanMsg,"CMD_RESP: HW spec command Failed\n");
break;
}
card->CurCmdRetCode = WLAN_STATUS_FAILURE;
rt_event_send(&(card->cmdwaitevent), CmdWaitQWoken);
return WLAN_STATUS_FAILURE;
}
switch (RespCmd)
{
case HostCmd_RET_MAC_REG_ACCESS:
case HostCmd_RET_BBP_REG_ACCESS:
case HostCmd_RET_RF_REG_ACCESS:
// ret = wlan_ret_reg_access(priv, RespCmd, resp);
break;
case HostCmd_RET_HW_SPEC_INFO:
ret = wlan_ret_get_hw_spec(card, resp);
break;
case HostCmd_RET_802_11_SCAN:
if (card->ScanPurpose == ScanMultichs)
{
ret = WlanparserScanResult(card, resp);
}
else if (card->ScanPurpose == ScanFilter)
{
ret = WlanparserScanResult(card, resp);
// ret = wlan_ret_802_11_scan(card, resp);
}
break;
case HostCmd_RET_MAC_CONTROL:
WlanDebug(WlanMsg,"HostCmd_RET_MAC_CONTROL\r\n");
break;
case HostCmd_RET_802_11_ASSOCIATE:
ret = wlan_ret_802_11_associate(card, resp);
break;
case HostCmd_RET_802_11_DEAUTHENTICATE:
// ret = wlan_ret_802_11_disassociate(priv, resp);
break;
case HostCmd_RET_802_11_SET_WEP:
ret = wlan_ret_802_11_set_wep(card, resp);
break;
case HostCmd_RET_802_11_RESET:
// ret = wlan_ret_802_11_reset(priv, resp);
break;
case HostCmd_RET_802_11_RF_TX_POWER:
ret = wlan_ret_802_11_rf_tx_power(card, resp);
break;
case HostCmd_RET_802_11_RADIO_CONTROL:
// ret = wlan_ret_802_11_radio_control(priv, resp);
break;
case HostCmd_RET_802_11_SNMP_MIB:
ret = wlan_ret_802_11_snmp_mib(card, resp);
break;
case HostCmd_RET_802_11_RF_ANTENNA:
// ret = wlan_ret_802_11_rf_antenna(priv, resp);
break;
case HostCmd_RET_MAC_MULTICAST_ADR:
ret = wlan_ret_mac_multicast_adr(card, resp);
break;
case HostCmd_RET_802_11_RATE_ADAPT_RATESET:
ret = wlan_ret_802_11_rate_adapt_rateset(card, resp);
break;
case HostCmd_RET_802_11_RF_CHANNEL:
// ret = wlan_ret_802_11_rf_channel(priv, resp);
break;
case HostCmd_RET_802_11_RSSI:
ret = wlan_ret_802_11_rssi(card, resp);
break;
case HostCmd_RET_802_11_GET_LOG:
ret = wlan_ret_802_11_get_log(card, resp);
break;
case HostCmd_RET_802_11_MAC_ADDRESS:
// ret = wlan_ret_802_11_mac_address(priv, resp);
break;
case HostCmd_RET_802_11_CAL_DATA_EXT:
// ret = wlan_ret_802_11_cal_data_ext(priv, resp);
break;
case HostCmd_RET_802_11_KEY_MATERIAL:
ret = wlan_ret_802_11_key_material(card, resp);
break;
case HostCmd_RET_CMD_GSPI_BUS_CONFIG:
WlanDebug(WlanMsg,"HostCmd_RET_CMD_GSPI_BUS_CONFIG\r\n");
break;
case HostCmd_RET_802_11D_DOMAIN_INFO:
// ret = wlan_ret_802_11d_domain_info(priv, resp);
break;
case HostCmd_RET_802_11_BCA_CONFIG_TIMESHARE:
// ret = wlan_ret_802_11_bca_timeshare(priv, resp);
break;
case HostCmd_RET_802_11_INACTIVITY_TIMEOUT:
// *((u16 *) Adapter->CurCmd->pdata_buf) =
// wlan_le16_to_cpu(resp->params.inactivity_timeout.Timeout);
break;
case HostCmd_RET_802_11_BG_SCAN_CONFIG:
break;
case HostCmd_RET_802_11_FW_WAKE_METHOD:
ret = wlan_ret_fw_wakeup_method(card, resp);
break;
case HostCmd_RET_802_11_SLEEP_PERIOD:
//ret = wlan_ret_802_11_sleep_period(priv, resp);
break;
case HostCmd_RET_WMM_GET_STATUS:
//ret = wlan_cmdresp_wmm_get_status(priv, resp);
break;
case HostCmd_RET_WMM_ADDTS_REQ:
// ret = wlan_cmdresp_wmm_addts_req(priv, resp);
break;
case HostCmd_RET_WMM_DELTS_REQ:
// ret = wlan_cmdresp_wmm_delts_req(priv, resp);
break;
case HostCmd_RET_WMM_QUEUE_CONFIG:
// ret = wlan_cmdresp_wmm_queue_config(priv, resp);
break;
case HostCmd_RET_WMM_QUEUE_STATS:
// ret = wlan_cmdresp_wmm_queue_stats(priv, resp);
break;
case HostCmd_CMD_TX_PKT_STATS:
// memcpy(Adapter->CurCmd->pdata_buf,
// &resp->params.txPktStats, sizeof(HostCmd_DS_TX_PKT_STATS));
// ret = WLAN_STATUS_SUCCESS;
break;
case HostCmd_RET_802_11_TPC_CFG:
// memmove(Adapter->CurCmd->pdata_buf,
// &resp->params.tpccfg, sizeof(HostCmd_DS_802_11_TPC_CFG));
break;
case HostCmd_RET_802_11_LED_CONTROL:
{
break;
}
case HostCmd_RET_802_11_CRYPTO:
//ret = wlan_ret_cmd_802_11_crypto(priv, resp);
break;
case HostCmd_RET_GET_TSF:
/*resp->params.gettsf.TsfValue =
wlan_le64_to_cpu(resp->params.gettsf.TsfValue);
memcpy(priv->adapter->CurCmd->pdata_buf,
&resp->params.gettsf.TsfValue, sizeof(u64));*/
break;
case HostCmd_RTE_802_11_TX_RATE_QUERY:
// priv->adapter->TxRate =
// wlan_le16_to_cpu(resp->params.txrate.TxRate);
break;
case HostCmd_RET_VERSION_EXT:
/* memcpy(Adapter->CurCmd->pdata_buf,
&resp->params.verext, sizeof(HostCmd_DS_VERSION_EXT));*/
break;
case HostCmd_RET_802_11_PS_MODE:
break;
default:
WlanDebug(WlanMsg,"CMD_RESP: Unknown command response %#x\n",resp->Command);
break;
}
if (card->CurCmd)
{
/* Clean up and Put current command back to CmdFreeQ */
rt_event_send(&(cardinfo->cmdwaitevent), CmdWaitQWoken);
}
done:
return ret;
}
void hm_tdc_thread_entry(void* parameter)
{
rt_device_t tdc = RT_NULL;
rt_uint8_t tof_data_count = 0;
rt_uint8_t temp_data_count = 0;
rt_uint8_t loop_count = TOF_DATA_BUF_LEN/TEMP_DATA_BUF_LEN;
tdc = rt_device_find(HM_BOARD_TDC_NAME);
RT_ASSERT(tdc);
rt_device_open(tdc, RT_DEVICE_OFLAG_RDWR);
#if (HM_BOARD_UART_6 == 1)
tt_print_device = rt_device_find(TOF_TEMP_PRINT_DEVICE);
RT_ASSERT(tt_print_device);
rt_device_open(tt_print_device, RT_DEVICE_OFLAG_RDWR);
#endif
tof_lock = rt_mutex_create("L_tof", RT_IPC_FLAG_FIFO);
RT_ASSERT(tof_lock);
temp_lock = rt_mutex_create("L_temp", RT_IPC_FLAG_FIFO);
RT_ASSERT(temp_lock);
while(1) {
loop_count--;
{ /* TOF */
if(rt_mutex_take(tof_lock, rt_tick_from_millisecond(LOCK_TACK_WAIT_TIME_MS)) != RT_EOK) {
rt_kprintf("TOF take lock error\n");
continue;
}
else {
rt_device_control(tdc, SPI_TDC_GP21_CTRL_MEASURE_TOF2, &tof_data[tof_data_count].data);
tof_data[tof_data_count].time = rt_tick_get();
rt_mutex_release(tof_lock);
tof_data_count++;
}
}
if(loop_count == 0) { /* TEMP */
loop_count = TOF_DATA_BUF_LEN/TEMP_DATA_BUF_LEN;
if(rt_mutex_take(temp_lock, rt_tick_from_millisecond(LOCK_TACK_WAIT_TIME_MS)) != RT_EOK) {
rt_kprintf("temprature take lock error\n");
continue;
}
else {
rt_device_control(tdc, SPI_TDC_GP21_CTRL_MEASURE_TEMP, &temp_data[temp_data_count].data);
temp_data[temp_data_count].time = rt_tick_get();
rt_mutex_release(temp_lock);
temp_data_count++;
}
}
if((temp_data_count==TEMP_DATA_BUF_LEN) || (tof_data_count==TOF_DATA_BUF_LEN)) { /* Send event */
temp_data_count = 0;
tof_data_count = 0;
if(rt_event_send(cal_event, TDC_DATA_FULL_EVENT) != RT_EOK) {
rt_kprintf("TDC send event error\n");
}
}
rt_thread_delay(rt_tick_from_millisecond(TDC_SLEEP_TIME_MS));
}
}
static rt_err_t can2ind(rt_device_t dev, void *args, rt_int32_t hdr, rt_size_t size)
{
rt_event_t pevent = (rt_event_t)args;
rt_event_send(pevent, 1 << (hdr));
return RT_EOK;
}
