int main()
{
target_init();
HAL_SET_PIN_DIRECTIONS();
wdt_disable();
led_on( LED_ALL );
hal_delay( 500 );
led_off( LED_ALL );
dbo_open(0, 38400);
TiRtc * rtc;
rtc = rtc_construct( (void *)&g_rtc, sizeof(g_rtc) );
rtc = rtc_open( rtc, NULL, NULL, 0x00 );
rtc_start( rtc );
while(1)
{}
// if not use listener
while (!rtc_expired(rtc))
{
//do something;
}
// rtc_expired now
}
/* int32_t open(const uint8_t* filename)
* calls open jump table
*
*
*/
int32_t open(const uint8_t* filename)
{
// uint32_t flags;
// cli_and_save(flags);
/* Get the current process */
pcb_t* cur_PCB = curr_process;
file_t* farray = cur_PCB->file_fds;
/* Find next open slot in the file array */
uint32_t fd = 0;
while(farray[fd].flags == 1)
fd++;
/* Check if there's space for the file and open a valid dentry*/
dentry_t dentry;
if(fd > 7 || -1 == read_dentry_by_name(filename, &dentry))
return -1;
file_t* cur_file = &(farray[fd]);
// Fill the file array entry
switch(dentry.file_type)
{
case 0: // RTC
if(-1 == rtc_open(cur_file, filename))
return -1;
break;
case 1: // Directory
if(-1 == dir_open(cur_file, filename))
return -1;
break;
case 2: // File
if(-1 == file_open(cur_file, filename))
return -1;
break;
default: // Invalid type
return -1;
}
return fd;
}
/* Check if MAGIC is valid and print the Multiboot information structure
pointed by ADDR. */
void
entry (unsigned long magic, unsigned long addr)
{
uint32_t fileptr;// start of file system
multiboot_info_t *mbi;
/* Initialize the screen. */
terminal_open();
/* Am I booted by a Multiboot-compliant boot loader? */
if (magic != MULTIBOOT_BOOTLOADER_MAGIC)
{
printf ("Invalid magic number: 0x%#x\n", (unsigned) magic);
return;
}
/* Set MBI to the address of the Multiboot information structure. */
mbi = (multiboot_info_t *) addr;
/* Print out the flags. */
printf ("flags = 0x%#x\n", (unsigned) mbi->flags);
/* Are mem_* valid? */
if (CHECK_FLAG (mbi->flags, 0))
printf ("mem_lower = %uKB, mem_upper = %uKB\n",
(unsigned) mbi->mem_lower, (unsigned) mbi->mem_upper);
/* Is boot_device valid? */
if (CHECK_FLAG (mbi->flags, 1))
printf ("boot_device = 0x%#x\n", (unsigned) mbi->boot_device);
/* Is the command line passed? */
if (CHECK_FLAG (mbi->flags, 2))
printf ("cmdline = %s\n", (char *) mbi->cmdline);
if (CHECK_FLAG (mbi->flags, 3)) {
int mod_count = 0;
int i;
module_t* mod = (module_t*)mbi->mods_addr;
fileptr = mod->mod_start;
while(mod_count < mbi->mods_count) {
printf("Module %d loaded at address: 0x%#x\n", mod_count, (unsigned int)mod->mod_start);
printf("Module %d ends at address: 0x%#x\n", mod_count, (unsigned int)mod->mod_end);
printf("First few bytes of module:\n");
for(i = 0; i<16; i++) {
printf("0x%x ", *((char*)(mod->mod_start+i)));
}
printf("\n");
mod_count++;
}
}
/* Bits 4 and 5 are mutually exclusive! */
if (CHECK_FLAG (mbi->flags, 4) && CHECK_FLAG (mbi->flags, 5))
{
printf ("Both bits 4 and 5 are set.\n");
return;
}
/* Is the section header table of ELF valid? */
if (CHECK_FLAG (mbi->flags, 5))
{
elf_section_header_table_t *elf_sec = &(mbi->elf_sec);
printf ("elf_sec: num = %u, size = 0x%#x,"
" addr = 0x%#x, shndx = 0x%#x\n",
(unsigned) elf_sec->num, (unsigned) elf_sec->size,
(unsigned) elf_sec->addr, (unsigned) elf_sec->shndx);
}
/* Are mmap_* valid? */
if (CHECK_FLAG (mbi->flags, 6))
{
memory_map_t *mmap;
printf ("mmap_addr = 0x%#x, mmap_length = 0x%x\n",
(unsigned) mbi->mmap_addr, (unsigned) mbi->mmap_length);
for (mmap = (memory_map_t *) mbi->mmap_addr;
(unsigned long) mmap < mbi->mmap_addr + mbi->mmap_length;
mmap = (memory_map_t *) ((unsigned long) mmap
+ mmap->size + sizeof (mmap->size)))
printf (" size = 0x%x, base_addr = 0x%#x%#x\n"
" type = 0x%x, length = 0x%#x%#x\n",
(unsigned) mmap->size,
(unsigned) mmap->base_addr_high,
(unsigned) mmap->base_addr_low,
(unsigned) mmap->type,
(unsigned) mmap->length_high,
(unsigned) mmap->length_low);
}
/* Construct an LDT entry in the GDT */
{
seg_desc_t the_ldt_desc;
the_ldt_desc.granularity = 0;
the_ldt_desc.opsize = 1;
the_ldt_desc.reserved = 0;
the_ldt_desc.avail = 0;
the_ldt_desc.present = 1;
the_ldt_desc.dpl = 0x0;
the_ldt_desc.sys = 0;
the_ldt_desc.type = 0x2;
SET_LDT_PARAMS(the_ldt_desc, &ldt, ldt_size);
ldt_desc_ptr = the_ldt_desc;
lldt(KERNEL_LDT);
}
/* Construct a TSS entry in the GDT */
{
seg_desc_t the_tss_desc;
the_tss_desc.granularity = 0;
the_tss_desc.opsize = 0;
the_tss_desc.reserved = 0;
the_tss_desc.avail = 0;
the_tss_desc.seg_lim_19_16 = TSS_SIZE & 0x000F0000;
the_tss_desc.present = 1;
the_tss_desc.dpl = 0x0;
the_tss_desc.sys = 0;
the_tss_desc.type = 0x9;
the_tss_desc.seg_lim_15_00 = TSS_SIZE & 0x0000FFFF;
SET_TSS_PARAMS(the_tss_desc, &tss, tss_size);
tss_desc_ptr = the_tss_desc;
tss.ldt_segment_selector = KERNEL_LDT;
tss.ss0 = KERNEL_DS;
tss.esp0 = 0x800000;
ltr(KERNEL_TSS);
}
/* Mask all IRQs again*/
int j;
for(j=0;j<16;j++)
{
disable_irq(j);
}
/* Init the PIC */
i8259_init();
/* Init IDT vector 0-20*/
{
int i;
for(i=0;i<20;i++)
{
if(i!=15)
{
//Define an idt_desc_t structure
idt_desc_t idt_desc;
//populate w/ correct values
idt_desc.seg_selector=0x0010;
idt_desc.present=1;
idt_desc.size=1;
idt_desc.dpl=0x0;
idt_desc.reserved1=1;
idt_desc.reserved2=1;
idt_desc.reserved3=1;
SET_IDT_ENTRY(idt_desc, ehandlers[i]);
//Set new entry in table
idt[i]=idt_desc;
}
}
}
/* Init IRQ Interrupts*/
//Timer Chip
{
//Define an idt_desc_t structure
idt_desc_t idt_desc;
//populate w/ correct values
idt_desc.seg_selector=0x0010;
idt_desc.present=1;
idt_desc.size=1;
idt_desc.dpl=0x0;
idt_desc.reserved1=1;
idt_desc.reserved2=1;
SET_IDT_ENTRY(idt_desc, irqhandlers[0]);
//Set new entry in table
idt[32]=idt_desc;
//Disable IRQ masking
//enable_irq(0);
}
//Keyboard
{
//Define an idt_desc_t structure
idt_desc_t idt_desc;
//populate w/ correct values
idt_desc.seg_selector=0x0010;
idt_desc.present=1;
idt_desc.size=1;
idt_desc.dpl=0x0;
idt_desc.reserved1=1;
idt_desc.reserved2=1;
SET_IDT_ENTRY(idt_desc, irqhandlers[1]);
//Set new entry in table
idt[33]=idt_desc;
//Disable IRQ masking
//enable_irq(1);
}
//Real Time Clock
{
//Define an idt_desc_t structure
idt_desc_t idt_desc;
//populate w/ correct values
idt_desc.seg_selector=0x0010;
idt_desc.present=1;
idt_desc.size=1;
idt_desc.dpl=0x0;
idt_desc.reserved1=1;
idt_desc.reserved2=1;
SET_IDT_ENTRY(idt_desc, irqhandlers[2]);
//Set new entry in table
idt[40]=idt_desc;
//Disable IRQ masking
//enable_irq(8);
}
/* Init System Call 0x80 */
//Define an idt_desc_t structure
idt_desc_t idt_desc;
//populate w/ correct values
idt_desc.seg_selector=0x0010;
idt_desc.present=1;
idt_desc.size=1;
idt_desc.dpl=0x0;
idt_desc.reserved1=1;
idt_desc.reserved2=1;
SET_IDT_ENTRY(idt_desc, systemcall);
//Set new entry in table
idt[128]=idt_desc;
//Load new IDT
lidt(idt_desc_ptr);
/* Initialize devices, memory, filesystem, enable device interrupts on the
* PIC, any other initialization stuff... */
paging_init();
//Enable IRQ interrupts.
enable_irq(8);
enable_irq(2);
enable_irq(1);
/* Enable interrupts */
/* Do not enable the following until after you have set up your
* IDT correctly otherwise QEMU will triple fault and simple close
* without showing you any output */
printf("Enabling Interrupts\n");
sti();
/* This will be replaced by a system call after CP3 */
rtc_open();
filesys_init(fileptr); // start of filesystem
while(1)
{
printf("Reading-> ");
uint8_t buf[1024];
int cnt = terminal_read(buf, 1024);
buf[cnt] = '\0';
puts ((int8_t*)"Typed: ");
puts ((int8_t*)buf);
putc('\n');
}
/* Execute the first program (`shell') ... */
/* Spin (nicely, so we don't chew up cycles) */
asm volatile(".1: hlt; jmp .1;");
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1, or <0 on an error
*
* Notes: None
*
**********************************************************************/
int c_entry(void)
{
SWIM_WINDOW_T win1;
COLOR_T *fblog;
INT_32 lcddev;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Setup miscellaneous board functions */
phy3250_board_init();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install RTC interrupt handler as a IRQ interrupts */
int_install_irq_handler(IRQ_RTC, (PFV) rtc_user_interrupt);
/* Open RTC */
rtcdev = rtc_open(RTC, 0);
if (rtcdev == 0)
{
/* Error */
return -1;
}
/* Set a 1s match rate */
secs = lsecs = 0;
mstp.match_num = 0;
mstp.use_match_int = TRUE;
mstp.enable_onsw = FALSE;
mstp.match_tick_val = secs + 1;
rtc_ioctl(rtcdev, RTC_ENABLE, 0);
rtc_ioctl(rtcdev, RTC_SET_COUNT, 0);
rtc_ioctl(rtcdev, RTC_CLEAR_INTS, RTC_MATCH0_INT_STS);
rtc_ioctl(rtcdev, RTC_SETUP_MATCH, (INT_32) &mstp);
/* Setup LCD muxing for STN Color 16BPP */
clkpwr_setup_lcd(CLKPWR_LCDMUX_TFT16, 1);
/* Enable clock to LCD block (HCLK_EN)*/
clkpwr_clk_en_dis(CLKPWR_LCD_CLK, 1);
/* Setup LCD paramaters in the LCD controller */
lcddev = lcd_open(CLCDC, (INT_32) & LCD_DISPLAY);
/* Upper Panel Frame Base Address register */
lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF);
/* Enable LCD controller and power signals */
lcd_ioctl(lcddev, LCD_PWENABLE, 1);
/* Enable LCD backlight */
phy3250_lcd_backlight_enable(TRUE);
/* Enable LCD power */
phy3250_lcd_power_enable(TRUE);
/* Set frame buffer address */
fblog = (COLOR_T *) cp15_map_physical_to_virtual(PHY_LCD_FRAME_BUF);
/* Create a SWIM window */
swim_window_open(&win1, LCD_DISPLAY.pixels_per_line,
LCD_DISPLAY.lines_per_panel, fblog, 0, 0,
(LCD_DISPLAY.pixels_per_line - 1), (LCD_DISPLAY.lines_per_panel - 1),
1, WHITE, BLACK, BLACK);
swim_put_ltext(&win1, "RTC example: This example will print the message "
"TICK whenever an RTC interrupt occurs (1 second intervals). It will "
"quit after 10 seconds\n");
/* Enable RTC (starts counting) */
rtc_ioctl(rtcdev, RTC_ENABLE, 1);
/* Enable RTC interrupt in the interrupt controller */
int_enable(IRQ_RTC);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Loop for 10 seconds and let interrupts toggle the LEDs */
while (secs < 10)
{
if (lsecs < secs)
{
swim_put_ltext(&win1, "TICK\n");
lsecs = secs;
}
}
/* Disable RTC interrupt in the interrupt controller */
int_disable(IRQ_RTC);
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Prior to closing the RTC, the ONSW key value is set. This will
allow the RTC to keep it's value across resets as long as RTC
power is maintained */
rtc_ioctl(rtcdev, RTC_SETCLR_KEY, 1);
/* Close RTC and LCD */
rtc_close(rtcdev);
lcd_close(lcddev);
return 1;
}
/*
* sys_rtc_open
* Description: open system RTC
* INPUTS:
const uint8_t* filename -- file name
pcb_t* mypcb -- Process control block
* OUTPUTS: None
* RETURN: None
* SIDE EFFECTS: None
*/
extern int32_t sys_rtc_open(const uint8_t* filename, pcb_t* mypcb)
{
return rtc_open(filename);
}
