static int order_queue_worker(void *arg) { ORDER_WORKER_INIT; struct rte_event ev; while (t->err == false) { uint16_t event = rte_event_dequeue_burst(dev_id, port, &ev, 1, 0); if (!event) { if (rte_atomic64_read(outstand_pkts) <= 0) break; rte_pause(); continue; } if (ev.queue_id == 0) { /* from ordered queue */ order_queue_process_stage_0(&ev); while (rte_event_enqueue_burst(dev_id, port, &ev, 1) != 1) rte_pause(); } else if (ev.queue_id == 1) { /* from atomic queue */ order_process_stage_1(t, &ev, nb_flows, expected_flow_seq, outstand_pkts); } else { order_process_stage_invalid(t, &ev); } } return 0; }
static int perf_atq_worker(void *arg, const int enable_fwd_latency) { PERF_WORKER_INIT; struct rte_event ev; while (t->done == false) { uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0); if (!event) { rte_pause(); continue; } if (enable_fwd_latency && !prod_timer_type) /* first stage in pipeline, mark ts to compute fwd latency */ atq_mark_fwd_latency(&ev); /* last stage in pipeline */ if (unlikely((ev.sub_event_type % nb_stages) == laststage)) { if (enable_fwd_latency) cnt = perf_process_last_stage_latency(pool, &ev, w, bufs, sz, cnt); else cnt = perf_process_last_stage(pool, &ev, w, bufs, sz, cnt); } else { atq_fwd_event(&ev, sched_type_list, nb_stages); while (rte_event_enqueue_burst(dev, port, &ev, 1) != 1) rte_pause(); } } return 0; }
static int perf_atq_worker_burst(void *arg, const int enable_fwd_latency) { PERF_WORKER_INIT; uint16_t i; /* +1 to avoid prefetch out of array check */ struct rte_event ev[BURST_SIZE + 1]; while (t->done == false) { uint16_t const nb_rx = rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0); if (!nb_rx) { rte_pause(); continue; } for (i = 0; i < nb_rx; i++) { if (enable_fwd_latency && !prod_timer_type) { rte_prefetch0(ev[i+1].event_ptr); /* first stage in pipeline. * mark time stamp to compute fwd latency */ atq_mark_fwd_latency(&ev[i]); } /* last stage in pipeline */ if (unlikely((ev[i].sub_event_type % nb_stages) == laststage)) { if (enable_fwd_latency) cnt = perf_process_last_stage_latency( pool, &ev[i], w, bufs, sz, cnt); else cnt = perf_process_last_stage(pool, &ev[i], w, bufs, sz, cnt); ev[i].op = RTE_EVENT_OP_RELEASE; } else { atq_fwd_event(&ev[i], sched_type_list, nb_stages); } } uint16_t enq; enq = rte_event_enqueue_burst(dev, port, ev, nb_rx); while (enq < nb_rx) { enq += rte_event_enqueue_burst(dev, port, ev + enq, nb_rx - enq); } } return 0; }
static int order_queue_worker_burst(void *arg) { ORDER_WORKER_INIT; struct rte_event ev[BURST_SIZE]; uint16_t i; while (t->err == false) { uint16_t const nb_rx = rte_event_dequeue_burst(dev_id, port, ev, BURST_SIZE, 0); if (nb_rx == 0) { if (rte_atomic64_read(outstand_pkts) <= 0) break; rte_pause(); continue; } for (i = 0; i < nb_rx; i++) { if (ev[i].queue_id == 0) { /* from ordered queue */ order_queue_process_stage_0(&ev[i]); } else if (ev[i].queue_id == 1) {/* from atomic queue */ order_process_stage_1(t, &ev[i], nb_flows, expected_flow_seq, outstand_pkts); ev[i].op = RTE_EVENT_OP_RELEASE; } else { order_process_stage_invalid(t, &ev[i]); } } uint16_t enq; enq = rte_event_enqueue_burst(dev_id, port, ev, nb_rx); while (enq < nb_rx) { enq += rte_event_enqueue_burst(dev_id, port, ev + enq, nb_rx - enq); } } return 0; }