void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
u8 reg_bw_opmode;
u8 reg_prsr_rsc;
RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
("Switch to %s bandwidth\n",
rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
"20MHz" : "40MHz"))
if (is_hal_stop(rtlhal)) {
rtlphy->set_bwmode_inprogress = false;
return;
}
reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
switch (rtlphy->current_chan_bw) {
case HT_CHANNEL_WIDTH_20:
reg_bw_opmode |= BW_OPMODE_20MHZ;
rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
break;
case HT_CHANNEL_WIDTH_20_40:
reg_bw_opmode &= ~BW_OPMODE_20MHZ;
rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
reg_prsr_rsc =
(reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
break;
}
switch (rtlphy->current_chan_bw) {
case HT_CHANNEL_WIDTH_20:
rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
break;
case HT_CHANNEL_WIDTH_20_40:
rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
(mac->cur_40_prime_sc >> 1));
rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
(mac->cur_40_prime_sc ==
HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
break;
}
rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
rtlphy->set_bwmode_inprogress = false;
RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
}
static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw);
if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
if (dm_digtable->rssi_val_min <= 25)
dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_LowRssi;
else
dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_HighRssi;
} else {
if (dm_digtable->rssi_val_min <= 20)
dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_LowRssi;
else
dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_HighRssi;
}
} else {
dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
}
if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
dm_digtable->cur_cck_fa_state =
CCK_FA_STAGE_High;
else
dm_digtable->cur_cck_fa_state =
CCK_FA_STAGE_LOW;
if (dm_digtable->pre_cck_fa_state !=
dm_digtable->cur_cck_fa_state) {
if (dm_digtable->cur_cck_fa_state ==
CCK_FA_STAGE_LOW)
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
0x83);
else
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
0xcd);
dm_digtable->pre_cck_fa_state =
dm_digtable->cur_cck_fa_state;
}
rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
} else {
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
}
dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
}
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
"CCKPDStage=%x\n", dm_digtable->cur_cck_pd_state);
}
int rtl92su_hw_init(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
int err = 0;
bool rtstatus = true;
u8 i;
int wdcapra_add[] = {
REG_EDCA_BE_PARAM, REG_EDCA_BK_PARAM,
REG_EDCA_VI_PARAM, REG_EDCA_VO_PARAM};
u8 secr_value = 0x0;
/* 1. MAC Initialize */
/* Before FW download, we have to set some MAC register */
err = _rtl92su_macconfig_before_fwdownload(hw);
if (err) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
"Failed to get the device ready for the firmware (%d)\n",
err);
return err;
}
rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
REG_PMC_FSM) >> 16) & 0xF);
/* 2. download firmware */
rtstatus = rtl92s_download_fw(hw);
if (!rtstatus) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
"Failed to download FW. Init HW without FW now... Please copy FW into /lib/firmware/rtlwifi\n");
return -ENOENT;
}
/* After FW download, we have to reset MAC register */
_rtl92su_macconfig_after_fwdownload(hw);
/*Retrieve default FW Cmd IO map. */
rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, REG_LBUS_MON_ADDR);
rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, REG_LBUS_ADDR_MASK);
/* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
rtstatus = rtl92s_phy_mac_config(hw);
if (!rtstatus) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
return -EINVAL;
}
/* because last function modify RCR, so we update
* rcr var here, or TP will unstable for receive_config
* is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
* RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
*/
/* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
/* We must set flag avoid BB/RF config period later!! */
rtl_write_word(rtlpriv, CMDR, 0x37FC);
/* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
rtstatus = rtl92s_phy_bb_config(hw);
if (!rtstatus) {
RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
return -ENODEV;
}
/* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
/* Before initalizing RF. We can not use FW to do RF-R/W. */
rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
/* Before RF-R/W we must execute the IO from Scott's suggestion. */
rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0xDB);
if (rtlhal->version == VERSION_8192S_ACUT)
rtl_write_byte(rtlpriv, REG_SPS1_CTRL + 3, 0x07);
else
rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07);
rtstatus = rtl92s_phy_rf_config(hw);
if (!rtstatus) {
RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
return -EOPNOTSUPP;
}
/* After read predefined TXT, we must set BB/MAC/RF
* register as our requirement */
rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
(enum radio_path)0,
RF_CHNLBW,
RFREG_OFFSET_MASK);
rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
(enum radio_path)1,
RF_CHNLBW,
RFREG_OFFSET_MASK);
/*---- Set CCK and OFDM Block "ON"----*/
rtl_set_bbreg(hw, REG_RFPGA0_RFMOD, BCCKEN, 0x1);
rtl_set_bbreg(hw, REG_RFPGA0_RFMOD, BOFDMEN, 0x1);
/*3 Set Hardware(Do nothing now) */
_rtl92su_hw_configure(hw);
/* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
/* TX power index for different rate set. */
/* Get original hw reg values */
rtl92s_phy_get_hw_reg_originalvalue(hw);
/* Write correct tx power index */
rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
/* We must set MAC address after firmware download. */
for (i = 0; i < 6; i++)
rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
/* We enable high power and RA related mechanism after NIC
* initialized. */
if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
/* Fw v.53 and later. */
rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
} else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
/* Fw v.52. */
rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_INIT);
rtl92s_phy_chk_fwcmd_iodone(hw);
} else {
/* Compatible earlier FW version. */
rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_RESET);
rtl92s_phy_chk_fwcmd_iodone(hw);
rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_ACTIVE);
rtl92s_phy_chk_fwcmd_iodone(hw);
rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_REFRESH);
rtl92s_phy_chk_fwcmd_iodone(hw);
}
/* Security related
* 1. Clear all H/W keys.
* 2. Enable H/W encryption/decryption. */
rtl_cam_reset_all_entry(hw);
secr_value |= SCR_TXENCENABLE;
secr_value |= SCR_RXENCENABLE;
secr_value |= SCR_NOSKMC;
rtl_write_byte(rtlpriv, REG_SECR, secr_value);
for (i = 0; i < 4; i++)
rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
if (rtlphy->rf_type == RF_1T2R) {
bool mrc2set = true;
/* Turn on B-Path */
rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
}
rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
rtl92s_dm_init(hw);
return err;
}
void rtl8821au_phy_rf6052_set_cck_txpower(struct rtl_priv *rtlpriv, uint8_t *pPowerlevel)
{
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_efuse *efuse = rtl_efuse(rtlpriv);
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
struct mlme_ext_priv *pmlmeext = &rtlpriv->mlmeextpriv;
uint32_t TxAGC[2] = {0, 0},
tmpval = 0;
BOOLEAN TurboScanOff = _FALSE;
uint8_t idx1, idx2;
uint8_t *ptr;
/* FOR CE ,must disable turbo scan */
TurboScanOff = _TRUE;
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
TxAGC[RF90_PATH_A] = 0x3f3f3f3f;
TxAGC[RF90_PATH_B] = 0x3f3f3f3f;
TurboScanOff = _TRUE; /* disable turbo scan */
if (TurboScanOff) {
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
/* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
if (TxAGC[idx1] > 0x20 && rtlhal->external_pa_5g)
TxAGC[idx1] = 0x20;
}
}
} else {
/*
* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
*/
if (rtlpriv->dm.dynamic_txhighpower_lvl == TxHighPwrLevel_Level1) {
TxAGC[RF90_PATH_A] = 0x10101010;
TxAGC[RF90_PATH_B] = 0x10101010;
} else if (rtlpriv->dm.dynamic_txhighpower_lvl == TxHighPwrLevel_Level2) {
TxAGC[RF90_PATH_A] = 0x00000000;
TxAGC[RF90_PATH_B] = 0x00000000;
} else {
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
}
if (efuse->eeprom_regulatory == 0) {
tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
(rtlphy->mcs_txpwrlevel_origoffset[0][7]<<8);
TxAGC[RF90_PATH_A] += tmpval;
tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
(rtlphy->mcs_txpwrlevel_origoffset[0][15]<<24);
TxAGC[RF90_PATH_B] += tmpval;
}
}
}
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
ptr = (uint8_t *)(&(TxAGC[idx1]));
for (idx2 = 0; idx2 < 4; idx2++) {
if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR;
ptr++;
}
}
/* rf-A cck tx power */
tmpval = TxAGC[RF90_PATH_A]&0xff;
rtl_set_bbreg(rtlpriv, RTXAGC_A_CCK11_CCK1, MASKBYTE1, tmpval);
/* RT_DISP(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32)); */
tmpval = TxAGC[RF90_PATH_A]>>8;
rtl_set_bbreg(rtlpriv, RTXAGC_A_CCK11_CCK1, 0xffffff00, tmpval);
/* RT_DISP(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); */
/* rf-B cck tx power */
tmpval = TxAGC[RF90_PATH_B]>>24;
rtl_set_bbreg(rtlpriv, RTXAGC_B_CCK11_CCK1, MASKBYTE0, tmpval);
/* RT_DISP(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); */
tmpval = TxAGC[RF90_PATH_B]&0x00ffffff;
rtl_set_bbreg(rtlpriv, RTXAGC_B_CCK11_CCK1, 0xffffff00, tmpval);
/* RT_DISP(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK1_55_Mcs32)); */
} /* PHY_RF6052SetCckTxPower */
void odm_Adaptivity(struct rtl_priv *rtlpriv, u8 IGI)
{
struct _rtw_hal *pHalData = GET_HAL_DATA(rtlpriv);
struct _rtw_dm *pDM_Odm = &pHalData->odmpriv;
struct dig_t *dm_digtable = &(rtlpriv->dm_digtable);
int32_t TH_H_dmc, TH_L_dmc;
int32_t TH_H, TH_L, Diff, IGI_target;
bool EDCCA_State;
RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "odm_Adaptivity() =====> \n");
if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
pDM_Odm->TH_H = 0xf4; /* 0xf8; */
pDM_Odm->TH_L = 0xf7; /* 0xfb; */
} else {
pDM_Odm->TH_H = 0xf4; /* 0xfa; */
pDM_Odm->TH_L = 0xf7; /* 0xfd; */
}
RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "pDM_Odm->ForceEDCCA=%d, IGI_Base=0x%x, TH_H=0x%x, TH_L=0x%x, AdapEn_RSSI = %d\n",
pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_H, pDM_Odm->TH_L, pDM_Odm->AdapEn_RSSI);
rtl_set_bbreg(pDM_Odm->rtlpriv, 0x800, BIT(10), 0); /* ADC_mask enable */
if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
return;
}
if (!pDM_Odm->ForceEDCCA) {
if (dm_digtable->rssi_val_min > pDM_Odm->AdapEn_RSSI)
EDCCA_State = 1;
else if (dm_digtable->rssi_val < (pDM_Odm->AdapEn_RSSI - 5))
EDCCA_State = 0;
} else
EDCCA_State = 1;
/*
* if ((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (*pDM_Odm->pBandType == BAND_ON_5G))
* IGI_target = pDM_Odm->IGI_Base;
* else
*/
if (rtlpriv->phy.current_chan_bw == CHANNEL_WIDTH_20) /*CHANNEL_WIDTH_20 */
IGI_target = pDM_Odm->IGI_Base;
else if (rtlpriv->phy.current_chan_bw == CHANNEL_WIDTH_40)
IGI_target = pDM_Odm->IGI_Base + 2;
else if (rtlpriv->phy.current_chan_bw == CHANNEL_WIDTH_80)
IGI_target = pDM_Odm->IGI_Base + 6;
else
IGI_target = pDM_Odm->IGI_Base;
pDM_Odm->IGI_target = IGI_target;
if (pDM_Odm->TH_H & BIT(7))
TH_H = pDM_Odm->TH_H | 0xFFFFFF00;
else
TH_H = pDM_Odm->TH_H;
if (pDM_Odm->TH_L & BIT(7))
TH_L = pDM_Odm->TH_L | 0xFFFFFF00;
else
TH_L = pDM_Odm->TH_L;
RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",
(rtlpriv->phy.current_chan_bw == CHANNEL_WIDTH_80) ? "80M" : ((rtlpriv->phy.current_chan_bw == CHANNEL_WIDTH_40) ? "40M" : "20M"), IGI_target, EDCCA_State);
if (EDCCA_State == 1) {
if (IGI < IGI_target) {
Diff = IGI_target - (int32_t)IGI;
TH_H_dmc = TH_H + Diff;
if (TH_H_dmc > 10)
TH_H_dmc = 10;
TH_L_dmc = TH_L + Diff;
if (TH_L_dmc > 10)
TH_L_dmc = 10;
} else {
Diff = (int32_t)IGI - IGI_target;
TH_H_dmc = TH_H - Diff;
TH_L_dmc = TH_L - Diff;
}
TH_H_dmc = (TH_H_dmc & 0xFF);
TH_L_dmc = (TH_L_dmc & 0xFF);
} else {
TH_H_dmc = 0x7f;
TH_L_dmc = 0x7f;
}
RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "IGI=0x%x, TH_H_dmc=0x%x, TH_L_dmc=0x%x\n",
IGI, TH_H_dmc, TH_L_dmc);
rtl_set_bbreg(pDM_Odm->rtlpriv, rFPGA0_XB_LSSIReadBack, 0xFFFF, (TH_H_dmc<<8) | TH_L_dmc);
}
static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
{
u32 ret_value;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
unsigned long flag = 0;
/* hold ofdm counter */
rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */
rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */
ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, BMASKDWORD);
falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, BMASKDWORD);
falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, BMASKDWORD);
falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, BMASKDWORD);
falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
falsealm_cnt->cnt_rate_illegal +
falsealm_cnt->cnt_crc8_fail +
falsealm_cnt->cnt_mcs_fail +
falsealm_cnt->cnt_fast_fsync_fail +
falsealm_cnt->cnt_sb_search_fail;
if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
/* hold cck counter */
rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, BMASKBYTE0);
falsealm_cnt->cnt_cck_fail = ret_value;
ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, BMASKBYTE3);
falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
} else {
falsealm_cnt->cnt_cck_fail = 0;
}
/* reset false alarm counter registers */
falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
falsealm_cnt->cnt_sb_search_fail +
falsealm_cnt->cnt_parity_fail +
falsealm_cnt->cnt_rate_illegal +
falsealm_cnt->cnt_crc8_fail +
falsealm_cnt->cnt_mcs_fail +
falsealm_cnt->cnt_cck_fail;
rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
/* update ofdm counter */
rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
/* update page C counter */
rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
/* update page D counter */
rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
/* reset cck counter */
rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
/* enable cck counter */
rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
}
RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("Cnt_Fast_Fsync_fail = %x, "
"Cnt_SB_Search_fail = %x\n",
falsealm_cnt->cnt_fast_fsync_fail,
falsealm_cnt->cnt_sb_search_fail));
RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("Cnt_Parity_Fail = %x, "
"Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, "
"Cnt_Mcs_fail = %x\n",
falsealm_cnt->cnt_parity_fail,
falsealm_cnt->cnt_rate_illegal,
falsealm_cnt->cnt_crc8_fail,
falsealm_cnt->cnt_mcs_fail));
RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
("Cnt_Ofdm_fail = %x, " "Cnt_Cck_fail = %x, "
"Cnt_all = %x\n",
falsealm_cnt->cnt_ofdm_fail,
falsealm_cnt->cnt_cck_fail,
falsealm_cnt->cnt_all));
}
void rtl8723be_phy_rf6052_set_cck_txpower( struct ieee80211_hw *hw,
u8 *ppowerlevel )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_phy *rtlphy = &( rtlpriv->phy );
struct rtl_mac *mac = rtl_mac( rtl_priv( hw ) );
struct rtl_efuse *rtlefuse = rtl_efuse( rtl_priv( hw ) );
u32 tx_agc[2] = {0, 0}, tmpval;
bool turbo_scanoff = false;
u8 idx1, idx2;
u8 *ptr;
u8 direction;
u32 pwrtrac_value;
if ( rtlefuse->eeprom_regulatory != 0 )
turbo_scanoff = true;
if ( mac->act_scanning ) {
tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
if ( turbo_scanoff ) {
for ( idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++ ) {
tx_agc[idx1] = ppowerlevel[idx1] |
( ppowerlevel[idx1] << 8 ) |
( ppowerlevel[idx1] << 16 ) |
( ppowerlevel[idx1] << 24 );
}
}
} else {
for ( idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++ ) {
tx_agc[idx1] = ppowerlevel[idx1] |
( ppowerlevel[idx1] << 8 ) |
( ppowerlevel[idx1] << 16 ) |
( ppowerlevel[idx1] << 24 );
}
if ( rtlefuse->eeprom_regulatory == 0 ) {
tmpval =
( rtlphy->mcs_txpwrlevel_origoffset[0][6] ) +
( rtlphy->mcs_txpwrlevel_origoffset[0][7] << 8 );
tx_agc[RF90_PATH_A] += tmpval;
tmpval = ( rtlphy->mcs_txpwrlevel_origoffset[0][14] ) +
( rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
24 );
tx_agc[RF90_PATH_B] += tmpval;
}
}
for ( idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++ ) {
ptr = ( u8 * )( &( tx_agc[idx1] ) );
for ( idx2 = 0; idx2 < 4; idx2++ ) {
if ( *ptr > RF6052_MAX_TX_PWR )
*ptr = RF6052_MAX_TX_PWR;
ptr++;
}
}
rtl8723be_dm_txpower_track_adjust( hw, 1, &direction, &pwrtrac_value );
if ( direction == 1 ) {
tx_agc[0] += pwrtrac_value;
tx_agc[1] += pwrtrac_value;
} else if ( direction == 2 ) {
tx_agc[0] -= pwrtrac_value;
tx_agc[1] -= pwrtrac_value;
}
tmpval = tx_agc[RF90_PATH_A] & 0xff;
rtl_set_bbreg( hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_A_CCK1_MCS32 );
tmpval = tx_agc[RF90_PATH_A] >> 8;
/*tmpval = tmpval & 0xff00ffff;*/
rtl_set_bbreg( hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK11_A_CCK2_11 );
tmpval = tx_agc[RF90_PATH_B] >> 24;
rtl_set_bbreg( hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK11_A_CCK2_11 );
tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
rtl_set_bbreg( hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK1_55_MCS32 );
}
static bool _rtl8723be_phy_rf6052_config_parafile( struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_phy *rtlphy = &( rtlpriv->phy );
u32 u4_regvalue = 0;
u8 rfpath;
bool rtstatus = true;
struct bb_reg_def *pphyreg;
for ( rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++ ) {
pphyreg = &rtlphy->phyreg_def[rfpath];
switch ( rfpath ) {
case RF90_PATH_A:
case RF90_PATH_C:
u4_regvalue = rtl_get_bbreg( hw, pphyreg->rfintfs,
BRFSI_RFENV );
break;
case RF90_PATH_B:
case RF90_PATH_D:
u4_regvalue = rtl_get_bbreg( hw, pphyreg->rfintfs,
BRFSI_RFENV << 16 );
break;
}
rtl_set_bbreg( hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1 );
udelay( 1 );
rtl_set_bbreg( hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1 );
udelay( 1 );
rtl_set_bbreg( hw, pphyreg->rfhssi_para2,
B3WIREADDREAALENGTH, 0x0 );
udelay( 1 );
rtl_set_bbreg( hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0 );
udelay( 1 );
switch ( rfpath ) {
case RF90_PATH_A:
rtstatus = rtl8723be_phy_config_rf_with_headerfile( hw,
( enum radio_path )rfpath );
break;
case RF90_PATH_B:
rtstatus = rtl8723be_phy_config_rf_with_headerfile( hw,
( enum radio_path )rfpath );
break;
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
switch ( rfpath ) {
case RF90_PATH_A:
case RF90_PATH_C:
rtl_set_bbreg( hw, pphyreg->rfintfs,
BRFSI_RFENV, u4_regvalue );
break;
case RF90_PATH_B:
case RF90_PATH_D:
rtl_set_bbreg( hw, pphyreg->rfintfs,
BRFSI_RFENV << 16, u4_regvalue );
break;
}
if ( !rtstatus ) {
RT_TRACE( rtlpriv, COMP_INIT, DBG_TRACE,
"Radio[%d] Fail!!", rfpath );
return false;
}
}
RT_TRACE( rtlpriv, COMP_INIT, DBG_TRACE, "\n" );
return rtstatus;
}
static void _rtl92s_dm_initial_gain_sta_beforeconnect(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
static u8 initialized, force_write;
u8 initial_gain = 0;
if ((digtable.pre_sta_connectstate == digtable.cur_sta_connectstate) ||
(digtable.cur_sta_connectstate == DIG_STA_BEFORE_CONNECT)) {
if (digtable.cur_sta_connectstate == DIG_STA_BEFORE_CONNECT) {
if (rtlpriv->psc.rfpwr_state != ERFON)
return;
if (digtable.backoff_enable_flag)
rtl92s_backoff_enable_flag(hw);
else
digtable.backoff_val = DM_DIG_BACKOFF;
if ((digtable.rssi_val + 10 - digtable.backoff_val) >
digtable.rx_gain_range_max)
digtable.cur_igvalue =
digtable.rx_gain_range_max;
else if ((digtable.rssi_val + 10 - digtable.backoff_val)
< digtable.rx_gain_range_min)
digtable.cur_igvalue =
digtable.rx_gain_range_min;
else
digtable.cur_igvalue = digtable.rssi_val + 10 -
digtable.backoff_val;
if (falsealm_cnt->cnt_all > 10000)
digtable.cur_igvalue =
(digtable.cur_igvalue > 0x33) ?
digtable.cur_igvalue : 0x33;
if (falsealm_cnt->cnt_all > 16000)
digtable.cur_igvalue =
digtable.rx_gain_range_max;
/* connected -> connected or disconnected -> disconnected */
} else {
/* Firmware control DIG, do nothing in driver dm */
return;
}
/* disconnected -> connected or connected ->
* disconnected or beforeconnect->(dis)connected */
} else {
/* Enable FW DIG */
digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_ENABLE);
digtable.backoff_val = DM_DIG_BACKOFF;
digtable.cur_igvalue = rtlpriv->phy.default_initialgain[0];
digtable.pre_igvalue = 0;
return;
}
/* Forced writing to prevent from fw-dig overwriting. */
if (digtable.pre_igvalue != rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1,
MASKBYTE0))
force_write = 1;
if ((digtable.pre_igvalue != digtable.cur_igvalue) ||
!initialized || force_write) {
/* Disable FW DIG */
rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_DISABLE);
initial_gain = (u8)digtable.cur_igvalue;
/* Set initial gain. */
rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, initial_gain);
rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, initial_gain);
digtable.pre_igvalue = digtable.cur_igvalue;
initialized = 1;
force_write = 0;
}
}
static void _rtl8723e_write_ofdm_power_reg( struct ieee80211_hw *hw,
u8 index, u32 *pvalue )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_phy *rtlphy = &rtlpriv->phy;
u16 regoffset_a[6] = {
RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
};
u16 regoffset_b[6] = {
RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
};
u8 i, rf, pwr_val[4];
u32 writeval;
u16 regoffset;
for ( rf = 0; rf < 2; rf++ ) {
writeval = pvalue[rf];
for ( i = 0; i < 4; i++ ) {
pwr_val[i] = ( u8 )( ( writeval & ( 0x7f <<
( i * 8 ) ) ) >> ( i * 8 ) );
if ( pwr_val[i] > RF6052_MAX_TX_PWR )
pwr_val[i] = RF6052_MAX_TX_PWR;
}
writeval = ( pwr_val[3] << 24 ) | ( pwr_val[2] << 16 ) |
( pwr_val[1] << 8 ) | pwr_val[0];
if ( rf == 0 )
regoffset = regoffset_a[index];
else
regoffset = regoffset_b[index];
rtl_set_bbreg( hw, regoffset, MASKDWORD, writeval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"Set 0x%x = %08x\n", regoffset, writeval );
if ( ( ( get_rf_type( rtlphy ) == RF_2T2R ) &&
( regoffset == RTXAGC_A_MCS15_MCS12 ||
regoffset == RTXAGC_B_MCS15_MCS12 ) ) ||
( ( get_rf_type( rtlphy ) != RF_2T2R ) &&
( regoffset == RTXAGC_A_MCS07_MCS04 ||
regoffset == RTXAGC_B_MCS07_MCS04 ) ) ) {
writeval = pwr_val[3];
if ( regoffset == RTXAGC_A_MCS15_MCS12 ||
regoffset == RTXAGC_A_MCS07_MCS04 )
regoffset = 0xc90;
if ( regoffset == RTXAGC_B_MCS15_MCS12 ||
regoffset == RTXAGC_B_MCS07_MCS04 )
regoffset = 0xc98;
for ( i = 0; i < 3; i++ ) {
writeval = ( writeval > 6 ) ? ( writeval - 6 ) : 0;
rtl_write_byte( rtlpriv, ( u32 ) ( regoffset + i ),
( u8 )writeval );
}
}
}
}