static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr) { u32 reg; rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); if (!rtsx_vendor_setting_valid(reg)) return; pcr->aspm_en = rtsx_reg_to_aspm(reg); pcr->sd30_drive_sel_1v8 = map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg)); pcr->sd30_drive_sel_3v3 = map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg)); }
static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr) { u32 reg1 = 0; u8 reg3 = 0; rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®1); pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); if (!rtsx_vendor_setting_valid(reg1)) return; pcr->aspm_en = rtsx_reg_to_aspm(reg1); pcr->sd30_drive_sel_1v8 = map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); pcr->card_drive_sel &= 0x3F; pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); rtsx_pci_read_config_byte(pcr, PCR_SETTING_REG3, ®3); pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3); pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3); }
static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) { struct rtsx_cr_option *option = &pcr->option; u32 lval; rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_5260, &lval); if (lval & ASPM_L1_1_EN_MASK) rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); if (lval & ASPM_L1_2_EN_MASK) rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); if (lval & PM_L1_1_EN_MASK) rtsx_set_dev_flag(pcr, PM_L1_1_EN); if (lval & PM_L1_2_EN_MASK) rtsx_set_dev_flag(pcr, PM_L1_2_EN); rts5260_pwr_saving_setting(pcr); if (option->ltr_en) { u16 val; pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); if (val & PCI_EXP_DEVCTL2_LTR_EN) { option->ltr_enabled = true; option->ltr_active = true; rtsx_set_ltr_latency(pcr, option->ltr_active_latency); } else { option->ltr_enabled = false; } } if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN | PM_L1_1_EN | PM_L1_2_EN)) option->force_clkreq_0 = false; else option->force_clkreq_0 = true; }