static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) { struct rtsx_cr_option *option = &pcr->option; u32 lval; rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_5260, &lval); if (lval & ASPM_L1_1_EN_MASK) rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); if (lval & ASPM_L1_2_EN_MASK) rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); if (lval & PM_L1_1_EN_MASK) rtsx_set_dev_flag(pcr, PM_L1_1_EN); if (lval & PM_L1_2_EN_MASK) rtsx_set_dev_flag(pcr, PM_L1_2_EN); rts5260_pwr_saving_setting(pcr); if (option->ltr_en) { u16 val; pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); if (val & PCI_EXP_DEVCTL2_LTR_EN) { option->ltr_enabled = true; option->ltr_active = true; rtsx_set_ltr_latency(pcr, option->ltr_active_latency); } else { option->ltr_enabled = false; } } if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN | PM_L1_1_EN | PM_L1_2_EN)) option->force_clkreq_0 = false; else option->force_clkreq_0 = true; }
static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) { struct rtsx_cr_option *option = &(pcr->option); u32 lval; if (CHK_PCI_PID(pcr, PID_524A)) rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_REG1, &lval); else rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_REG2, &lval); if (lval & ASPM_L1_1_EN_MASK) rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); if (lval & ASPM_L1_2_EN_MASK) rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); if (lval & PM_L1_1_EN_MASK) rtsx_set_dev_flag(pcr, PM_L1_1_EN); if (lval & PM_L1_2_EN_MASK) rtsx_set_dev_flag(pcr, PM_L1_2_EN); if (option->ltr_en) { u16 val; pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); if (val & PCI_EXP_DEVCTL2_LTR_EN) { option->ltr_enabled = true; option->ltr_active = true; rtsx_set_ltr_latency(pcr, option->ltr_active_latency); } else { option->ltr_enabled = false; } } }