int proc_get_rf_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
int len = 0;
len += snprintf(page + len, count - len, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n"
"oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n",
pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset,
rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter));
*eof = 1;
return len;
}
VOID
odm_Adaptivity(
IN PDM_ODM_T pDM_Odm
)
{
#ifdef CONFIG_ODM_ADAPTIVITY
s1Byte TH_L2H_dmc, TH_H2L_dmc;
s1Byte Diff, IGI_target;
u32 value32;
BOOLEAN EDCCA_State = 0;
_adapter *pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *dmpriv = &pHalData->dmpriv;
DIG_T *pDigTable = &dmpriv->DM_DigTable;
u8 IGI = pDigTable->CurIGValue;
u8 RSSI_Min = pDigTable->Rssi_val_min;
HT_CHANNEL_WIDTH BandWidth = rtw_get_oper_bw(pAdapter);
if (!(dmpriv->DMFlag & DYNAMIC_FUNC_ADAPTIVITY))
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
// Add by Neil Chen to enable edcca to MP Platform
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
// Adjust EDCCA.
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
odm_DynamicEDCCA(pDM_Odm);
#endif
return;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable
if(!dm_linked(pAdapter) || pHalData->CurrentChannel > 149) // Band4 doesn't need adaptivity
{
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, 0x7f);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, 0x7f);
}
else
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, (0x7f<<8) | 0x7f);
return;
}
#if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
if(pMgntInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0a);
else
ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0e);
#endif
if(!pDM_Odm->ForceEDCCA)
{
if(RSSI_Min > pDM_Odm->AdapEn_RSSI)
EDCCA_State = 1;
else if(RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5))
EDCCA_State = 0;
}
else
EDCCA_State = 1;
//if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (*pDM_Odm->pBandType == BAND_ON_5G))
//IGI_target = pDM_Odm->IGI_Base;
//else
{
if(BandWidth == HT_CHANNEL_WIDTH_20) //CHANNEL_WIDTH_20
IGI_target = pDM_Odm->IGI_Base;
else if(BandWidth == HT_CHANNEL_WIDTH_40)
IGI_target = pDM_Odm->IGI_Base + 2;
/*else if(*pDM_Odm->pBandWidth == ODM_BW80M)
IGI_target = pDM_Odm->IGI_Base + 6;*/
else
IGI_target = pDM_Odm->IGI_Base;
}
pDM_Odm->IGI_target = (u1Byte) IGI_target;
//Search pwdB lower bound
if(pDM_Odm->TxHangFlg == _TRUE)
{
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
odm_SearchPwdBLowerBound(pDM_Odm, IGI_target);
}
if(dm_linked(pAdapter) && pDM_Odm->TxHangFlg == _FALSE &&pDM_Odm->NHM_disable == _FALSE)
odm_NHMBB(pDM_Odm);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",
(BandWidth==HT_CHANNEL_WIDTH_40)?"40M":"20M", IGI_target, EDCCA_State));
if(EDCCA_State == 1)
{
Diff = IGI_target -(s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if(TH_L2H_dmc > 10) TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
//replace lower bound to prevent EDCCA always equal 1
if(TH_H2L_dmc < pDM_Odm->H2L_lb)
TH_H2L_dmc = pDM_Odm->H2L_lb;
if(TH_L2H_dmc < pDM_Odm->L2H_lb)
TH_L2H_dmc = pDM_Odm->L2H_lb;
}
else
{
TH_L2H_dmc = 0x7f;
TH_H2L_dmc = 0x7f;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n",
IGI, TH_L2H_dmc, TH_H2L_dmc));
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
}
else
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u1Byte)TH_H2L_dmc<<8) | (u1Byte)TH_L2H_dmc);
#endif /* CONFIG_ODM_ADAPTIVITY */
}
