int s3c_gpio_set_slewrate(unsigned int pin, unsigned int config) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); void __iomem *reg; unsigned long flags; int offset; u32 con; int shift; if (!chip) return -EINVAL; if (config > S3C_GPIO_SLEWRATE_SLOW) return -EINVAL; reg = chip->base + 0x0c; offset = pin - chip->chip.base; shift = offset; local_irq_save(flags); con = __raw_readl(reg); con &= ~(1 << shift); con |= config << shift; __raw_writel(con, reg); #ifdef S5PC11X_ALIVEGPIO_STORE con = __raw_readl(reg); #endif local_irq_restore(flags); return 0; }
unsigned int s3c2410_gpio_getpin(unsigned int pin) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); unsigned long offs = pin - chip->chip.base; return __raw_readl(chip->base + 0x04) & (1<< offs); }
/* S5PV210 machine dependent GPIO help function */ int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); void __iomem *reg; unsigned long flags; int offset; u32 con; int shift; if (!chip) return -EINVAL; if ((pin <= S5PV210_GPH3(7)) && (pin >= S5PV210_GPH0(0))) return -EINVAL; if (config > S3C_GPIO_SLP_PREV) return -EINVAL; reg = chip->base + 0x10; offset = pin - chip->chip.base; shift = offset * 2; local_irq_save(flags); con = __raw_readl(reg); con &= ~(3 << shift); con |= config << shift; __raw_writel(con, reg); local_irq_restore(flags); return 0; }
s3c_gpio_pull_t s3c_gpio_slp_getpull_updown(unsigned int pin) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); void __iomem *reg; unsigned long flags; int offset; u32 con; int shift; if (!chip) return -EINVAL; if((chip->base == (S3C64XX_GPK_BASE + 0x4)) || (chip->base == (S3C64XX_GPL_BASE + 0x4)) || (chip->base == S3C64XX_GPM_BASE) || (chip->base == S3C64XX_GPN_BASE)) { return -EINVAL; } reg = chip->base + 0x10; offset = pin - chip->chip.base; shift = offset * 2; local_irq_save(flags); con = __raw_readl(reg); con >>= shift; con &= 0x3; local_irq_restore(flags); return (__force s3c_gpio_pull_t)con; }
int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); void __iomem *reg; unsigned long flags; int offset; u32 con; int shift; if (!chip) return -EINVAL; if ((pin >= EXYNOS4_GPX0(0)) && (pin <= EXYNOS4_GPX3(7))) return -EINVAL; if (config > S3C_GPIO_PULL_UP) return -EINVAL; reg = chip->base + 0x14; offset = pin - chip->chip.base; shift = offset * 2; local_irq_save(flags); con = __raw_readl(reg); con &= ~(3 << shift); con |= config << shift; __raw_writel(con, reg); local_irq_restore(flags); return 0; }
int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); unsigned long offs = pin - chip->chip.base; unsigned long flags; unsigned long slpcon; offs *= 2; if (pin < S3C2410_GPB(0)) return -EINVAL; if (pin >= S3C2410_GPF(0) && pin <= S3C2410_GPG(16)) return -EINVAL; if (pin > S3C2410_GPH(16)) return -EINVAL; local_irq_save(flags); slpcon = __raw_readl(chip->base + 0x0C); slpcon &= ~(3 << offs); slpcon |= state << offs; __raw_writel(slpcon, chip->base + 0x0C); local_irq_restore(flags); return 0; }
s3c_gpio_pull_t s3c_gpio_get_slp_cfgpin(unsigned int pin) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); void __iomem *reg; unsigned long flags; int offset; u32 con; int shift; if (!chip) return -EINVAL; if ((pin >= EXYNOS4_GPX0(0)) && (pin <= EXYNOS4_GPX3(7))) return -EINVAL; reg = chip->base + 0x10; offset = pin - chip->chip.base; shift = offset * 2; local_irq_save(flags); con = __raw_readl(reg); con >>= shift; con &= 0x3; local_irq_restore(flags); return (__force s3c_gpio_pull_t)con; }
s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); unsigned long flags; int offset; u32 pup = 0; if (chip) { offset = pin - chip->chip.base; s3c_gpio_lock(chip, flags); pup = s3c_gpio_do_getpull(chip, offset); s3c_gpio_unlock(chip, flags); } return (__force s3c_gpio_pull_t)pup; }
unsigned s3c_gpio_getcfg(unsigned int pin) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); unsigned long flags; unsigned ret = 0; int offset; if (chip) { offset = pin - chip->chip.base; s3c_gpio_lock(chip, flags); ret = s3c_gpio_do_getcfg(chip, offset); s3c_gpio_unlock(chip, flags); } return ret; }
int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); unsigned long flags; int offset, ret; if (!chip) return -EINVAL; offset = pin - chip->chip.base; local_irq_save(flags); ret = s3c_gpio_do_setpull(chip, offset, pull); local_irq_restore(flags); return ret; }
int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); unsigned long flags; int offset, ret; if (!chip) return -EINVAL; offset = pin - chip->chip.base; s3c_gpio_lock(chip, flags); ret = s3c_gpio_do_setpull(chip, offset, pull); s3c_gpio_unlock(chip, flags); return ret; }
int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); unsigned long flags; int offset; int ret; if (!chip) return -EINVAL; offset = pin - chip->chip.base; local_irq_save(flags); ret = s3c_gpio_do_setcfg(chip, offset, config); local_irq_restore(flags); return ret; }
s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); void __iomem *reg; int shift = off * 2; u32 drvstr; if (!chip) return -EINVAL; reg = chip->base + 0x0C; drvstr = __raw_readl(reg); drvstr = 0xffff & (0x3 << shift); drvstr = drvstr >> shift; return (__force s5p_gpio_drvstr_t)drvstr; }
s3c_gpio_pull_t s3c_gpio_getpin(unsigned int pin) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); unsigned long flags; int offset; s3c_gpio_pull_t ret; if (!chip) return -EINVAL; offset = pin - chip->chip.base; local_irq_save(flags); //ret = s3c_gpio_do_getpin(chip, offset, level); ret = (chip->config->get_pin) (chip, offset); local_irq_restore(flags); return ret; }
int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, s5p_gpio_drvstr_t drvstr) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); void __iomem *reg; int shift = off * 2; u32 tmp; if (!chip) return -EINVAL; reg = chip->base + 0x0C; tmp = __raw_readl(reg); tmp |= drvstr << shift; __raw_writel(tmp, reg); return 0; }
s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); unsigned int off; void __iomem *reg; int shift; u32 drvstr; if (!chip) return -EINVAL; off = pin - chip->chip.base; shift = off * 2; reg = chip->base + 0x0C; drvstr = __raw_readl(reg); drvstr = drvstr >> shift; drvstr &= 0x3; return (__force s5p_gpio_drvstr_t)drvstr; }
int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config) { struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); void __iomem *reg; unsigned long flags; int offset; u32 con; int shift; if (!chip) return -EINVAL; if((chip->base == (S3C64XX_GPK_BASE + 0x4)) || (chip->base == (S3C64XX_GPL_BASE + 0x4)) || (chip->base == S3C64XX_GPM_BASE) || (chip->base == S3C64XX_GPN_BASE)) { return -EINVAL; } if(config > 3) { return -EINVAL; } reg = chip->base + 0x10; offset = pin - chip->chip.base; shift = offset * 2; local_irq_save(flags); con = __raw_readl(reg); con &= ~(3 << shift); con |= config << shift; __raw_writel(con, reg); con = __raw_readl(reg); local_irq_restore(flags); return 0; }