void __init_or_cpufreq exynos5_setup_clocks(void) { struct clk *xtal_clk; unsigned long apll; unsigned long bpll; unsigned long cpll; unsigned long mpll; unsigned long epll; unsigned long vpll; unsigned long vpllsrc; unsigned long xtal; unsigned long armclk; unsigned long mout_cdrex; unsigned long aclk_400; unsigned long aclk_333; unsigned long aclk_266; unsigned long aclk_200; unsigned long aclk_166; unsigned long aclk_66; unsigned int ptr; printk(KERN_DEBUG "%s: registering clocks\n", __func__); xtal_clk = clk_get(NULL, "xtal"); BUG_ON(IS_ERR(xtal_clk)); xtal = clk_get_rate(xtal_clk); xtal_rate = xtal; clk_put(xtal_clk); printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0)); bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0)); cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0)); mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0)); epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0), __raw_readl(EXYNOS5_EPLL_CON1)); vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk); vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0), __raw_readl(EXYNOS5_VPLL_CON1)); clk_fout_apll.ops = &exynos5_fout_apll_ops; clk_fout_bpll.rate = bpll; clk_fout_cpll.rate = cpll; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; clk_fout_vpll.rate = vpll; printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n" "M=%ld, E=%ld V=%ld", apll, bpll, cpll, mpll, epll, vpll); armclk = clk_get_rate(&exynos5_clk_armclk); mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk); aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk); aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk); aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk); aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk); aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk); aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk); printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n" "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n" "ACLK166=%ld, ACLK66=%ld\n", armclk, mout_cdrex, aclk_400, aclk_333, aclk_266, aclk_200, aclk_166, aclk_66); clk_fout_epll.ops = &exynos5_epll_ops; if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll)) printk(KERN_ERR "Unable to set parent %s of clock %s.\n", clk_fout_epll.name, exynos5_clk_mout_epll.clk.name); clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000); clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000); clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000); clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000); for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++) s3c_set_clksrc(&exynos5_clksrcs[ptr], true); }
void __init_or_cpufreq exynos4_setup_clocks(void) { struct clk *xtal_clk; unsigned long apll = 0; unsigned long mpll = 0; unsigned long epll = 0; unsigned long vpll = 0; unsigned long vpllsrc; unsigned long xtal; unsigned long armclk; unsigned long sclk_dmc; unsigned long aclk_200; unsigned long aclk_100; unsigned long aclk_160; unsigned long aclk_133; unsigned int ptr; printk(KERN_DEBUG "%s: registering clocks\n", __func__); xtal_clk = clk_get(NULL, "xtal"); BUG_ON(IS_ERR(xtal_clk)); xtal = clk_get_rate(xtal_clk); xtal_rate = xtal; clk_put(xtal_clk); printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); if (soc_is_exynos4210()) { apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), __raw_readl(S5P_EPLL_CON1), pll_4600); vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), __raw_readl(S5P_VPLL_CON1), pll_4650c); } else if (soc_is_exynos4212() || soc_is_exynos4412()) { apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0)); mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0)); epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0), __raw_readl(S5P_EPLL_CON1)); vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), __raw_readl(S5P_VPLL_CON1)); } else { /* nothing */ } clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; clk_fout_vpll.ops = &exynos4_vpll_ops; clk_fout_vpll.rate = vpll; printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", apll, mpll, epll, vpll); armclk = clk_get_rate(&clk_armclk.clk); sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); aclk_200 = clk_get_rate(&clk_aclk_200.clk); aclk_100 = clk_get_rate(&clk_aclk_100.clk); aclk_160 = clk_get_rate(&clk_aclk_160.clk); aclk_133 = clk_get_rate(&clk_aclk_133.clk); printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", armclk, sclk_dmc, aclk_200, aclk_100, aclk_160, aclk_133); clk_f.rate = armclk; clk_h.rate = sclk_dmc; clk_p.rate = aclk_100; for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); }