static int s5p_i2s_resume(struct snd_soc_dai *dai) { if (suspended_by_pm) { suspended_by_pm = 0; s5p_i2s_do_resume(dai); } return 0; }
void s5p_i2s_do_resume_stream(struct snd_pcm_substream *substream) { s5p_i2s_do_resume(&s3c64xx_i2s_v4_dai); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) tx_clk_enabled = 1; else rx_clk_enabled = 1; }
void s5p_i2s_do_resume_for_rp(void) { u32 clkdiv_audss; s5p_i2s_do_resume(&s3c64xx_i2s_v4_dai); srp_clk_enabled = 1; /* SRP ratio (0+1) = EPLL/1 = 181MHz BUS ratio (3+1) = SRP/4 = 181/4 = 45MHz */ clkdiv_audss = readl(S5P_CLKDIV_AUDSS); clkdiv_audss &= ~0x0FF; clkdiv_audss |= 0x030; writel(clkdiv_audss, S5P_CLKDIV_AUDSS); }
static int s5p_i2s_wr_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { pr_debug("iis: %s:\n", __func__); s5p_i2s_do_resume(dai); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) tx_clk_enabled = 1; else rx_clk_enabled = 1; #ifdef CONFIG_S5P_INTERNAL_DMA if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) s5p_i2s_startup(dai); #endif return 0; }
void s5p_i2s_do_resume_for_rp(void) { s5p_i2s_do_resume(s3c64xx_i2s_dai); }