예제 #1
0
/// \brief Main function of the progam.
///
/// It's the most important function.
/// Generate the NoC system instantiating the NoC1 component.
/// Windows users: check the simulation time using 2 SYSTEMTIME variables and the function GetSystemTime from "windows.h".
/// For testing or to generate waves: use the technique shown in the code between //#INIT_WAVE and //#FINISH_WAVE. If not interested in waves, it is possible to cancel that part of code.
int sc_main (int argc,char *argv[])
{
		

	NoC_WR *NoC1;
	NoC1=new NoC_WR("NoC1");

	

	//SYSTEMTIME now,now1;
  
	//#INIT_WAVE
	sc_trace_file* tracefile;
	tracefile=sc_create_vcd_trace_file("wave");

	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->clkL,"clkL");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->clkR,"clkR");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_datain,"L_datain");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_datain,"R_datain");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_dataout,"L_dataout");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_dataout,"R_dataout");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_strobe_s,"L_strobe_s");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_strobe_s,"R_strobe_s");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_datac_s,"L_datac_s");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_datac_s,"R_datac_s");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->rx_RtoL.save_register_N,"save_register_N");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->rx_RtoL.save_register_P,"save_register_P");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->rx_RtoL.saved_packet,"saved_packet");
	
	sc_trace_file* tracefile2;
	tracefile2=sc_create_vcd_trace_file("wave2");

	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->clkL,"clkL");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->clkR,"clkR");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_datain,"L_datain");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_datain,"R_datain");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_dataout,"L_dataout");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_dataout,"R_dataout");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_strobe_s,"L_strobe_s");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_strobe_s,"R_strobe_s");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_datac_s,"L_datac_s");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_datac_s,"R_datac_s");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->rx_LtoR.datac_container[0],"datac_container[0]");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->rx_LtoR.datac_container[1],"datac_container[1]");
	//#FINISH_WAVE

	//GetSystemTime(&now);
		
	sc_start(1000,SC_NS);
	
	//GetSystemTime(&now1);
	//cout<<(now1.wMilliseconds-now.wMilliseconds)<<endl;

	//#INIT_WAVE
	sc_close_vcd_trace_file(tracefile);
	sc_close_vcd_trace_file(tracefile2);
	//#FINISH_WAVE
	
	return 0;
}
예제 #2
0
int sc_main(int argc, char* argv[]) {

  sc_signal<int>  out_free ;
  sc_signal<int>  out_available ;
  sc_signal<bool> out_full ;
  sc_signal<bool> out_empty ;

  test_fifo u_test_fifo( "u_test_fifo" ) ;
  u_test_fifo.out_free     ( out_free );
  u_test_fifo.out_available( out_available );
  u_test_fifo.out_full     ( out_full );
  u_test_fifo.out_empty    ( out_empty );

  sc_trace_file * vcd_file;
  vcd_file = sc_create_vcd_trace_file( "test_fifo" );
  sc_trace( vcd_file , out_free      , "out_free" );
  sc_trace( vcd_file , out_available , "out_available" );
  sc_trace( vcd_file , out_full      , "out_full" );
  sc_trace( vcd_file , out_empty     , "out_empty" );

  sc_start(1000, SC_NS);

  sc_close_vcd_trace_file( vcd_file );

  return 0;
}
int sc_main(int argc, char* argv[])
{
    sc_signal<bool> din, dout;

    sc_clock clk("clk",10,SC_NS,0.5,0, SC_NS,false);    // Create a clock signal
    
    delta DUT("delta");             // Instantiate Device Under Test

    DUT.din(din);                       // Connect ports
    DUT.dout(dout);
    DUT.clk(clk);

    sc_trace_file *fp;                  // Create VCD file
    fp=sc_create_vcd_trace_file("wave");// open(fp), create wave.vcd file
    fp->set_time_unit(100, SC_PS);      // set tracing resolution to ns
    sc_trace(fp,clk,"clk");             // Add signals to trace file
    sc_trace(fp,DUT.q_s,"q_s");
    sc_trace(fp,din,"din");

    sc_trace(fp,dout,"dout");

    sc_start(31, SC_NS);                // Run simulation
    din=true;                           
    sc_start(31, SC_NS);                // Run simulation
    din=false;                          
    sc_start(31, SC_NS);                // Run simulation

    sc_close_vcd_trace_file(fp);        // close(fp)

    return 0;
}
예제 #4
0
int sc_main(int, char **)
{
	sc_signal<bool> a, b, f;
	sc_clock clk("Clk", 20, SC_NS);	// 时钟周期为 20ns
	
	// 分别定义模块 NAND 和 TB 的实例,并通过局部变量(如 a、b)将这两个实例连接起来
	nand NAND("NAND");
	NAND.A(a);
	NAND.B(b);
	NAND.F(f);

	tb TB("TB");
	TB.clk(clk);
	TB.a(a);
	TB.b(b);
	TB.f(f);

	// 生成仿真结果波形文件
	sc_trace_file *tf = sc_create_vcd_trace_file("NAND");
	sc_trace(tf, NAND.A, "A");
	sc_trace(tf, NAND.B, "B");
	sc_trace(tf, NAND.F, "F");
	sc_trace(tf, TB.clk, "CLK");
	sc_start(200, SC_NS);	// 仿真时长 200ns
	sc_close_vcd_trace_file(tf);

	return 0;
}
예제 #5
0
파일: sc_main.cpp 프로젝트: vlady8711/Xor
int sc_main(int argc, char* argv[]) {
	sc_signal<bool> input_1, input_2, output;
	sc_clock test_clock("TestClock", 10, SC_NS, 0.5);
	sc_trace_file *trace_file;
	
	stimulus stimulus_1("Stimulus");
	stimulus_1.input_1(input_1);
	stimulus_1.input_2(input_2);
	stimulus_1.clock(test_clock);
	
	monitor monitor_1("Monitor");
	monitor_1.input_1(input_1);
	monitor_1.input_2(input_2);
	monitor_1.output(output);
	monitor_1.clock(test_clock);

	xor_ xor_1("Xor");
	xor_1.input_1(input_1);
	xor_1.input_2(input_2);
	xor_1.output(output);

	trace_file = sc_create_vcd_trace_file("wave");


	sc_trace(trace_file, test_clock, "Clock");
	sc_trace(trace_file, input_1, "Input_1");
	sc_trace(trace_file, input_2, "Input_2");
	sc_trace(trace_file, output, "Output");

	sc_start();

	sc_close_vcd_trace_file(trace_file);

	return 0;
}
예제 #6
0
int sc_main (int argc, char * argv[]) {
    sc_clock clk ("my_clock",1,0.5);
	ControlUnitTest *control = new ControlUnitTest("ControlUnitTest");
	control->clock(clk.signal());
	
	
	sc_trace_file *tf = sc_create_vcd_trace_file("ControlUnitTest");
	sc_trace(tf,control->clock,"clock");
	sc_trace(tf,control->iRInput,"iRInput");
	sc_trace(tf,control->statusBit,"statusBit");
	sc_trace(tf,control->ulaOp,"ulaOP");
	sc_trace(tf,control->ulaOutDemuxSel,"ulaOutDemuxSel");
	sc_trace(tf,control->ulaInAMuxSel,"ulaInAMuxSel");
	sc_trace(tf,control->ulaInBMuxSel,"ulaInBMuxSel");
	sc_trace(tf,control->rfSel,"rfSel");
	sc_trace(tf,control->rfReadWriteBit,"rfReadWriteBit");
	sc_trace(tf,control->writeMemory,"writeMemory");
	sc_trace(tf,control->loadRA,"loadRA");
	sc_trace(tf,control->loadRB,"loadRB");
	sc_trace(tf,control->loadIR,"loadIR");
	sc_trace(tf,control->loadAR,"loadAR");
	sc_trace(tf,control->loadPC,"loadPC");
	sc_trace(tf,control->loadDR,"loadDR");	
	
	
	sc_start();
	
	sc_close_vcd_trace_file(tf);
	return 0;
	
}
예제 #7
0
파일: main.cpp 프로젝트: kaiserhaz/SystemC
/**
 * main
 */
int sc_main(int argc, char* argv[]) {

	sc_set_time_resolution(1, SC_PS);

	sc_clock clock("clk", 1, SC_NS);
	
	// Shift reg is declared but not implemented
	sc_signal<int> shiftreg_in;
	sc_signal<int> shiftreg_out;

	sc_trace_file *tf = sc_create_vcd_trace_file("wave");
	
	sc_write_comment(tf, "Simulation of Shift Reg at Elaboration Time Resolution");

	sc_trace(tf, clock, "Clock");
	sc_trace(tf, shiftreg_in, "shiftreg_in");
	sc_trace(tf, shiftreg_out, "shiftreg_out");

	sc_start(30, SC_NS);

	sc_close_vcd_trace_file(tf);

	system("pause");

	return 0;

}
예제 #8
0
int sc_main(int ac, char *av[])
{
  sc_trace_file *tf;
  sc_signal<bool> clock;
  sc_signal<int> I;
  sc_signal<char> C;
  sc_signal<float> F;
  sc_signal<sc_logic> L;

  proc1 P1("P1", clock, I, C, F, L);

  tf = sc_create_vcd_trace_file("test08");
  sc_trace(tf, clock, "Clock");
  sc_trace(tf, I, "Int", 32);
  sc_trace(tf, C, "Char", 8);
  sc_trace(tf, F, "Float");
  sc_trace(tf, L, "Logic");

  clock.write(0);
  sc_start(0, SC_NS);
  for (int i = 0; i< 10; i++) {
    clock.write(1);
    sc_start(10, SC_NS);
    clock.write(0);
    sc_start(10, SC_NS);
  }
  sc_close_vcd_trace_file( tf );
  return 0;
}
Dilate_16_16_1080_1920_s::~Dilate_16_16_1080_1920_s() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

    delete grp_filter_opr_dilate_kernel_16_16_unsigned_char_int_1080_1920_3_3_s_fu_51;
    delete grp_getStructuringElement_unsigned_char_int_int_3_3_s_fu_80;
}
예제 #10
0
int sc_main(int argc, char* argv[]) {
  sc_signal<bool> t_a, t_b, t_cin, t_sum, t_cout;

  full_adder f1 ("FullAdderWithHalfAdder");
  // Positional association:
  f1 << t_a << t_b << t_cin << t_sum << t_cout;

  driver d1 ("GenerateWaveforms");
  d1 << t_a << t_b << t_cin;

  monitor mo1 ("MonitorWaveforms");
  mo1 << t_a << t_b << t_cin << t_sum << t_cout;

  if (! mo1.outfile) {
    cerr << "ERROR: Unable to open output file," << " fa_with_ha.out!\n";
    return (-2);
  }

  sc_trace_file *tf = sc_create_vcd_trace_file ("full_adder");
  sc_trace(tf, t_a,"A");
  sc_trace(tf, t_b, "B");
  sc_trace(tf, t_cin, "CarryIn");
  sc_trace(tf, t_sum, "Sum");
  sc_trace(tf, t_cout, "CarryOut");

  sc_start(100, SC_NS);

  // mo1.outfile.close();

  // d1.infile.close();
  sc_close_vcd_trace_file (tf);

  return(0);
}
예제 #11
0
int sc_main(int argc, char* argv[])
{
	sc_signal <unsigned int> sinalA, sinalB, sinalC;
	sc_clock clock(" Clock", 10, SC_NS,0.5, 1, SC_NS);
	
	Estimulos est("Estimulos");
	Maior m("Maior");
	
	est.A(sinalA);
	est.B(sinalB);
	est.Clk(clock);
	
	m.A(sinalA);
	m.B(sinalB);
	m.C(sinalC);
	
	sc_trace_file* Tf;
	Tf = sc_create_vcd_trace_file("traces");
	sc_trace (Tf,sinalA,"A");
	sc_trace (Tf,sinalB,"B");
	sc_trace (Tf,sinalC,"C");
	sc_trace (Tf,clock,"Clk");
	
	sc_start();
	
	sc_close_vcd_trace_file(Tf);
	
	return 0;
}
예제 #12
0
void test_miniuart()
{
	sc_set_time_resolution(1, SC_NS);

	sc_signal<bool> sys_clk, reset, int_rx, int_tx, txd_rxd;
	sc_signal_resolved ce, rd, wr;
	sc_signal_rv<2> addr;
	sc_signal_rv<8> data_in;
	sc_signal_rv<8> data_out;

	MiniUart MiniUart_inst("MiniUart");
		MiniUart_inst.sys_clk(sys_clk);
		MiniUart_inst.reset(reset);
		MiniUart_inst.ce(ce);
		MiniUart_inst.rd(rd);	
		MiniUart_inst.wr(wr);	
		MiniUart_inst.addr(addr);	
		MiniUart_inst.data_in(data_in);	
		MiniUart_inst.data_out(data_out);	

		MiniUart_inst.int_rx(int_rx);	
		MiniUart_inst.int_tx(int_tx);

		MiniUart_inst.rxd(txd_rxd);	
		MiniUart_inst.txd(txd_rxd);	

	RTL_TestBench RTL_TestBench_inst("RTL_TestBench");
		RTL_TestBench_inst.sys_clk(sys_clk);
		RTL_TestBench_inst.reset(reset);
		RTL_TestBench_inst.ce(ce);
		RTL_TestBench_inst.rd(rd);	
		RTL_TestBench_inst.wr(wr);	
		RTL_TestBench_inst.addr(addr);	
		RTL_TestBench_inst.data_in(data_out);	
		RTL_TestBench_inst.data_out(data_in);	

		RTL_TestBench_inst.int_rx(int_rx);	
		RTL_TestBench_inst.int_tx(int_tx);

	sc_trace_file *tf = sc_create_vcd_trace_file("wave_miniuart");
	sc_write_comment(tf, "Simulation of Mini Uart");
	((vcd_trace_file*)tf)->set_time_unit(1,SC_NS);	// 10exp(-9) = 1 ns

	sc_trace(tf,sys_clk, "sys_clk");
	sc_trace(tf,reset,"reset");
	sc_trace(tf,ce,"ce");
	sc_trace(tf,rd,"rd");
	sc_trace(tf,wr,"wr");
	sc_trace(tf,addr,"addr");
	sc_trace(tf,data_in,"data_in");
	sc_trace(tf,data_out,"data_out");
	sc_trace(tf,int_rx,"int_rx");
	sc_trace(tf,int_tx,"int_tx");
	sc_trace(tf,txd_rxd,"txd_rxd");

	sc_start(8, SC_MS);

	sc_close_vcd_trace_file(tf);
}
예제 #13
0
axi_stream_gpio::~axi_stream_gpio() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

    mHdltvinHandle << "] " << endl;
    mHdltvoutHandle << "] " << endl;
    mHdltvinHandle.close();
    mHdltvoutHandle.close();
}
예제 #14
0
파일: fe_top.cpp 프로젝트: raghup17/bmm
fe_top::~fe_top() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

    mHdltvinHandle << "] " << endl;
    mHdltvoutHandle << "] " << endl;
    mHdltvinHandle.close();
    mHdltvoutHandle.close();
}
xillybus_wrapper::~xillybus_wrapper() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

    mHdltvinHandle << "] " << endl;
    mHdltvoutHandle << "] " << endl;
    mHdltvinHandle.close();
    mHdltvoutHandle.close();
}
예제 #16
0
MAT_Multiply::~MAT_Multiply() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

    mHdltvinHandle << "] " << endl;
    mHdltvoutHandle << "] " << endl;
    mHdltvinHandle.close();
    mHdltvoutHandle.close();
    delete MAT_Multiply_mul_32s_32s_32_6_U1;
}
예제 #17
0
파일: iosc.cpp 프로젝트: KapSteR/TIHSC
iosc::~iosc() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

    mHdltvinHandle << "] " << endl;
    mHdltvoutHandle << "] " << endl;
    mHdltvinHandle.close();
    mHdltvoutHandle.close();
    delete grp_iosc_timerThread_fu_78;
    delete grp_iosc_iosThread_fu_104;
}
예제 #18
0
targeted_function::~targeted_function() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

    mHdltvinHandle << "] " << endl;
    mHdltvoutHandle << "] " << endl;
    mHdltvinHandle.close();
    mHdltvoutHandle.close();
    delete targeted_function_rm_s_axi_U;
    delete targeted_function_mul_32s_32s_32_6_U0;
}
예제 #19
0
adders::~adders() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

    mHdltvinHandle << "] " << endl;
    mHdltvoutHandle << "] " << endl;
    mHdltvinHandle.close();
    mHdltvoutHandle.close();
    delete adders_add_32ns_32ns_32_8_U1;
    delete adders_add_32ns_32ns_32_8_U2;
}
예제 #20
0
파일: main.cpp 프로젝트: notti/embedded_lu
int sc_main(int argc, char* argv[]){

  sc_signal<bool> reset;
  sc_signal<bool> ld;
  sc_signal<bool> lshift;
  sc_signal<bool> rshift;
  sc_signal<bool> leftin;
  sc_signal<bool> rightin;
  sc_signal<sc_bv<8> > in;
  sc_signal<sc_bv<8> > out;
   
  sc_clock clk ("clk", 2, SC_US);	// a clock with a period of 2 �-sec
   
  shiftreg sr("sr0");
  sr.clk(clk);
  sr.reset(reset);
  sr.ld(ld);
  sr.lshift(lshift);
  sr.rshift(rshift);
  sr.leftin(leftin);
  sr.rightin(rightin);
  sr.in(in);
  sr.out(out);
  stim st("stim0");
  st.reset(reset);
  st.ld(ld);
  st.lshift(lshift);
  st.rshift(rshift);
  st.leftin(leftin);
  st.rightin(rightin);
  st.in(out);
  st.out(in);
  sc_trace_file *tf;				// Signal tracing
  tf=sc_create_vcd_trace_file("shiftreg");	// create new trace file
  tf->set_time_unit(0.5,SC_US);	// set time resolution to 0.5 �-sec (let's do a bit oversampling ;-))
  
  sc_trace(tf,clk,"clk");
  sc_trace(tf,reset,"reset");
  sc_trace(tf,ld,"ld");
  sc_trace(tf,lshift,"lshift");
  sc_trace(tf,rshift,"rshift");
  sc_trace(tf,leftin,"leftin");
  sc_trace(tf,rightin,"rightin");
  sc_trace(tf,in,"in");
  sc_trace(tf,out,"out");

  sc_start(100,SC_US);	// run the simulation for 100 �-sec
  
  sc_close_vcd_trace_file(tf);	// close trace file

return 0;

};
예제 #21
0
int sc_main(int argc, char* argv[])
{
    sc_signal<bool> s_sig;
    sc_signal<bool> q_sig, qn_sig;
    sc_clock clk_sig("TestClock", 10, SC_NS, 0.5);

    TestGenerator tg("test_generator");
    tg.s_out(s_sig);
    tg.clk(clk_sig);

//#define TEST_S_LATCH_V0
//#define TEST_S_LATCH_V1
#define TEST_S_LATCH_WITH_TWO_OUT

#ifdef TEST_S_LATCH_V0
    SLatchV0 DUT("SLatchV0");
#endif

#ifdef TEST_S_LATCH_V1
    SLatchV1 DUT("SLatchV1");
#endif

#ifdef TEST_S_LATCH_WITH_TWO_OUT
    SLatchWithTwoOut DUT("SLatchWithTwoOut");
#endif

    DUT.clk_in(clk_sig);
    DUT.set_in(s_sig);
#ifndef TEST_S_LATCH_V0
    DUT.q_out(q_sig);
    DUT.qn_out(qn_sig);
#endif

    sc_trace_file* p_trace_file;
    p_trace_file = sc_create_vcd_trace_file("traces");
    sc_trace(p_trace_file, s_sig  , "set" );
    sc_trace(p_trace_file, DUT.reset_sig  , "reset" );
    sc_trace(p_trace_file, clk_sig  , "clk" );
    sc_trace(p_trace_file, DUT.a_sig  , "a" );
    sc_trace(p_trace_file, DUT.b_sig  , "b" );
    sc_trace(p_trace_file, DUT.q_internal_sig  , "q_internal_sig" );
    sc_trace(p_trace_file, DUT.qn_internal_sig  , "qn_internal_sig" );
#ifndef TEST_S_LATCH_V0
    sc_trace(p_trace_file, q_sig  , "q_sig" );
    sc_trace(p_trace_file, qn_sig , "qn_sig" );
#endif

    cout << "start simulation for " << DUT.name() << endl;
    sc_start(70, SC_NS); 
    sc_close_vcd_trace_file(p_trace_file);
    return 0;
}
예제 #22
0
uc_simulation_config_t::~uc_simulation_config_t(){
	if(rtos_list != NULL){
/*		for(int i=0;i<(*rtos_list).size();i++){
			(*rtos_list)[i]->print_backtrace();
		}*/
		delete rtos_list;
		rtos_list = NULL;
	}
	if(vcd_file != NULL){	
		sc_close_vcd_trace_file(vcd_file);
		vcd_file = NULL;
	}
}
예제 #23
0
matrix_mul::~matrix_mul() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

    mHdltvinHandle << "] " << endl;
    mHdltvoutHandle << "] " << endl;
    mHdltvinHandle.close();
    mHdltvoutHandle.close();
    delete m_result_U;
    delete m_operand1_U;
    delete m_operand2_U;
    delete grp_matrix_mul_thread_fu_74;
}
예제 #24
0
int sc_main(int argc, char* argv[]) {

    sc_clock clk("clk",10,SC_NS);
    sc_signal<bool> enable, rw, clr, ci, co, zflag, oflag;
    sc_signal<sc_uint<16> > din0, din1, dout2;
    sc_signal<sc_uint<4> > op;

    sc_trace(fp,clk,"clk");             // Add signals to trace file
    sc_trace(fp,enable,"enable");
    sc_trace(fp,rw,"rw");
    sc_trace(fp,clr,"clr");
    sc_trace(fp,ci,"ci");
    sc_trace(fp,co,"co");
    sc_trace(fp,zflag,"zflag");
    sc_trace(fp,oflag,"oflag");
    sc_trace(fp,din0,"din0");
    sc_trace(fp,din1,"din1");
    sc_trace(fp,dout2,"dout2");
    sc_trace(fp,op,"op");

    //datapath
    datapath DATAPATH("datapath");
    DATAPATH.enable(enable);
    DATAPATH.rw(rw);
    DATAPATH.clk(clk);
    DATAPATH.clr(clr);
    DATAPATH.din0(din0);
    DATAPATH.din1(din1);
    DATAPATH.dout2(dout2);
    DATAPATH.ci(ci);
    DATAPATH.co(co);
    DATAPATH.zflag(zflag);
    DATAPATH.oflag(oflag);
    DATAPATH.op(op);

    //stim
    stim STIM("stim");
    STIM.clk(clk);
    STIM.enable(enable);
    STIM.rw(rw);
    STIM.clr(clr);
    STIM.din0(din0);
    STIM.din1(din1);
    STIM.ci(ci);
    STIM.op(op);
     
    sc_start(1000, SC_NS);   //start simulation
               
    sc_close_vcd_trace_file(fp);        // close wave.vcd
    return 0;                           // Return OK, no errors.
}  
예제 #25
0
int sc_main(int, char **)
{
	sc_signal<sc_uint<ENABLESIZE> > en_n;
	sc_signal<sc_uint<INPUTSIZE> > dataIn;
	sc_signal<sc_uint<SELECTSIZE> > selIn;
	sc_signal<sc_uint<OUTPUTSIZE> > dataOut;
	sc_signal<sc_uint<OUTPUTSIZE> > flag;
	sc_clock clk("Clk", 20, SC_NS);
	
	// Connect modules ------------------------------------------
	mux_8_1 MUX_8_1("MUX_8_1");
	MUX_8_1.en_n(en_n);
	MUX_8_1.dataIn(dataIn);
	MUX_8_1.selIn(selIn);
	MUX_8_1.dataOut(dataOut);
	MUX_8_1.flag(flag);

	tb TB("TB");
	TB.clk(clk);
	TB.en_n(en_n);
	TB.dataIn(dataIn);
	TB.selIn(selIn);
	TB.dataOut(dataOut);
	TB.flag(flag);

	// Initialize keys ------------------------------------------
	cout << "Setting up FHEW" << endl;
	FHEW::Setup();
	cout << "Generating secret key ... " << endl;
	//LWE::SecretKey LWEsk;
	LWE::KeyGen(LWEsk);
	cout << "Done." << endl;
	cout << "Generating evaluation key ... this may take a while ... " << endl;
	//FHEW::EvalKey Ek;
	FHEW::KeyGen(&Ek, LWEsk);
	cout << "Done." << endl << endl;

	// Create trace files ----------------------------------------
	sc_trace_file *tf = sc_create_vcd_trace_file("Mux_8_1");
	sc_trace(tf, MUX_8_1.en_n, "en_n");
	sc_trace(tf, MUX_8_1.dataIn, "dataIn");
	sc_trace(tf, MUX_8_1.selIn, "selIn");
	sc_trace(tf, MUX_8_1.dataOut, "dataOut");
	sc_trace(tf, MUX_8_1.flag, "flag");
	sc_trace(tf, TB.clk, "CLK");
	sc_start(400, SC_NS);
	sc_close_vcd_trace_file(tf);

	return 0;
}
예제 #26
0
int
sc_main(int argc, char *argv[])
{
    // sc_clock	clk1("clk1", 10, SC_NS, 0.5);
    // sc_clock	clk2("clk2", 12, SC_NS, 0.5);
    sc_signal<bool> clk1( "clk1" );
    sc_signal<bool> clk2( "clk2" );

    foo		FOO("FOO");

    FOO.clk1(clk1);
    FOO.clk2(clk2);

    sc_trace_file *tf = sc_create_vcd_trace_file("test");
    // sc_trace(tf, clk1.signal(), "clk1");
    // sc_trace(tf, clk2.signal(), "clk2");
    sc_trace(tf, clk1, "clk1");
    sc_trace(tf, clk2, "clk2");

    sc_start(0, SC_NS);

    clk1 = 0;                                         
    clk2 = 0;                                          // 0 ns
    sc_start(3, SC_NS);
    clk2 = 1;                                          // 3 ns +
    sc_start(2, SC_NS);
    clk1 = 1;                                          // 5 ns +
    sc_start(4, SC_NS);
    clk2 = 0;                                          // 9 ns
    sc_start(1, SC_NS);
    clk1 = 0;                                          // 10 ns
    sc_start(5, SC_NS);
    clk2 = 1;                                          // 15 ns +
    sc_start(0, SC_NS);
    clk1 = 1;                                          // 15 ns +
    sc_start(5, SC_NS);
    clk1 = 0;                                          // 20 ns
    sc_start(1, SC_NS);
    clk2 = 0;                                          // 21 ns
    sc_start(4, SC_NS);
    clk1 = 1;                                          // 25 ns +
    sc_start(2, SC_NS);
    clk2 = 1;                                          // 27 ns +
    sc_start(3, SC_NS);
    clk1 = 0;                                          // 30 ns

    sc_close_vcd_trace_file(tf);

    return 0;
}
예제 #27
0
파일: sc_main.cpp 프로젝트: whsatku/compsys
int sc_main(int argc, char* argv[])
{
    sc_signal<sc_uint<8> > ain, bin, ra, rb;
    sc_signal<sc_uint<16> > result ,rc;
    sc_signal<bool> ready, start;

    sc_clock clk("clk",10,SC_NS,0.5);   // Create a clock signal

    sc_trace(fp, clk, "clk");
    sc_trace(fp, ain, "A");
    sc_trace(fp, bin, "B");
    sc_trace(fp, result, "C");

    sc_trace(fp, ra, "RA");
    sc_trace(fp, rb, "RB");
    sc_trace(fp, rc, "RC");
    sc_trace(fp, ready, "Ready");
    sc_trace(fp, start, "Start");

    multiplier DUT("multiplier");                      // Instantiate Device Under Test
    DUT.ain(ain);
    DUT.bin(bin);
    DUT.ra(ra);
    DUT.rb(rb);
    DUT.rc(rc);
    DUT.ready(ready);
    DUT.start(start);
    DUT.result(result);
    DUT.clk(clk);

    stim STIM("stimulus");              // Instantiate stimulus generator
    STIM.clk(clk);  
    STIM.ain(ain);
    STIM.bin(bin);
    STIM.ready(ready);
    STIM.start(start);

    check CHECK("check");
    CHECK.clk(clk);
    CHECK.ain(ain);
    CHECK.bin(bin);
    CHECK.ready(ready);
    CHECK.result(result);

    sc_start(150, SC_NS);               // Run simulation
    sc_close_vcd_trace_file(fp);

    return 0;                           // Return OK, no errors.
}
int sc_main(int argc, char *argv[]) {

	sc_set_time_resolution(1.0, SC_NS);

	sc_clock clk("clock", 20.84, SC_NS);
	sc_signal<bool>	rst;
	sc_signal<bool> data_out_wr, oe_wr;
	sc_signal<sc_uint<8>> data_out, oe, data_in;
	sc_signal_rv<8> pins;

	gpio				i_gpio("GPIO");
	test_gpio			i_test("TEST");

	i_gpio.clk(clk);
	i_gpio.rst(rst);

	i_test.clk(clk);
	i_test.rst(rst);

	i_test.data_out(data_out);
	i_test.data_out_wr(data_out_wr);
	i_test.oe(oe);
	i_test.oe_wr(oe_wr);
	i_test.data_in(data_in);
	i_test.pin(pins);

	i_gpio.data_out(data_out);
	i_gpio.data_out_wr(data_out_wr);
	i_gpio.oe(oe);
	i_gpio.oe_wr(oe_wr);
	i_gpio.data_in(data_in);
	i_gpio.pin(pins);

#ifdef VCD_OUTPUT_ENABLE
	sc_trace_file *vcd_log = sc_create_vcd_trace_file("TEST_GPIO");
	sc_trace(vcd_log, clk, "Clk");
	sc_trace(vcd_log, rst, "Reset_n");
	sc_trace(vcd_log, pins, "Pins");
#endif

	srand((unsigned int)(time(NULL) & 0xffffffff));
	sc_start();

#ifdef VCD_OUTPUT_ENABLE
	sc_close_vcd_trace_file(vcd_log);
#endif

	return i_test.error_cnt;
}
예제 #29
0
int sc_main(int argc, char* argv[])
{
    sc_signal<sc_int<4> > ain, bin, sum;
    sc_signal<bool> ci,co,zflag,oflag;

    sc_clock clk("clk",10,SC_NS,0.5);

    adder4 DUT("addsub4");
    DUT.ain(ain);
    DUT.bin(bin);
    DUT.ci(ci); 
    DUT.sum(sum);
    DUT.co(co);
    DUT.zf(zflag);
    DUT.of(oflag);

    stim STIM("stimulus");
    STIM.clk(clk);
    STIM.ain(ain);
    STIM.bin(bin);
    STIM.ci(ci);

    check CHECK("checker");
    CHECK.clk(clk); 
    CHECK.ain(ain);
    CHECK.bin(bin);
    CHECK.ci(ci);
    CHECK.sum(sum);
    CHECK.co(co);
    CHECK.zflag(zflag);
    CHECK.oflag(oflag);

    sc_initialize();
    sc_trace_file *tf = sc_create_vcd_trace_file("trace");

    sc_trace(tf, ain, "ain"); 
    sc_trace(tf, bin, "bin");
    sc_trace(tf, ci, "add/sub"); 
    sc_trace(tf, sum, "sum");
    sc_trace(tf, co, "co");
    sc_trace(tf, clk, "clk");
    sc_trace(tf, zflag, "zero_flag");
    sc_trace(tf, oflag, "overflow_flag");

    sc_start(200, SC_NS);    
    sc_close_vcd_trace_file(tf);

    return 0;                           // Return OK, no errors.
}
예제 #30
0
파일: sc_main.cpp 프로젝트: whsatku/compsys
int sc_main(int argc, char* argv[])
{
    sc_signal<sc_uint<4> > ain, bin, sum;
    sc_signal<bool> ci,co, zflag, oflag;

    sc_clock clk("clk",10,SC_NS,0.5);   // Create a clock signal

    sc_trace_file *fp=sc_create_vcd_trace_file("wave");
    sc_trace(fp, clk, "clk");
    sc_trace(fp, ain, "ain");
    sc_trace(fp, bin, "bin");
    sc_trace(fp, sum, "sum");
    sc_trace(fp, ci, "ci");
    sc_trace(fp, co, "co");
    sc_trace(fp, zflag, "zflag");
    sc_trace(fp, oflag, "oflag");

    adder DUT("adder");                 // Instantiate Device Under Test
    DUT.ain(ain);                       // Connect ports
    DUT.bin(bin);
    DUT.ci(ci);
    DUT.sum(sum);
    DUT.co(co);
    DUT.zflag(zflag);
    DUT.oflag(oflag);

    stim STIM("stimulus");              // Instantiate stimulus generator
    STIM.clk(clk);
    STIM.ain(ain);
    STIM.bin(bin);
    STIM.ci(ci);

    check CHECK("checker");             // Instantiate checker
    CHECK.clk(clk);
    CHECK.ain(ain);
    CHECK.bin(bin);
    CHECK.ci(ci);
    CHECK.sum(sum);
    CHECK.co(co);
    CHECK.zflag(zflag);
    CHECK.oflag(oflag);

    sc_start(100, SC_NS);               // Run simulation
    sc_close_vcd_trace_file(fp);

    return 0;                           // Return OK, no errors.
}