/*
* Function responsible for formatting parameters to pass from NS world to
* S world
*/
u32 omap4_secure_dispatcher(u32 app_id, u32 flags, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4)
{
u32 ret;
unsigned long iflags;
u32 pub2sec_args[5] = {0, 0, 0, 0, 0};
/*dpr_info("%s: app_id=0x%08x, flags=0x%08x, nargs=%u\n",
__func__, app_id, flags, nargs);*/
/*if (nargs != 0)
dpr_info("%s: args=%08x, %08x, %08x, %08x\n",
__func__, arg1, arg2, arg3, arg4);*/
pub2sec_args[0] = nargs;
pub2sec_args[1] = arg1;
pub2sec_args[2] = arg2;
pub2sec_args[3] = arg3;
pub2sec_args[4] = arg4;
/* Make sure parameters are visible to the secure world */
dmac_flush_range((void *)pub2sec_args,
(void *)(((u32)(pub2sec_args)) + 5*sizeof(u32)));
outer_clean_range(__pa(pub2sec_args),
__pa(pub2sec_args) + 5*sizeof(u32));
wmb();
/*
* Put L4 Secure clock domain to SW_WKUP so that modules are accessible
*/
clkdm_wakeup(smc_l4_sec_clkdm);
local_irq_save(iflags);
/* proc_id is always 0 */
ret = schedule_secure_world(app_id, 0, flags, __pa(pub2sec_args));
local_irq_restore(iflags);
/* Restore the HW_SUP on L4 Sec clock domain so hardware can idle */
if ((app_id != API_HAL_HWATURNOFF_INDEX) &&
(!timer_pending(&tf_crypto_clock_timer))) {
(void) tf_crypto_turn_off_clocks();
clkdm_allow_idle(smc_l4_sec_clkdm);
}
/*dpr_info("%s()\n", __func__);*/
return ret;
}
/*
* Function responsible for formatting parameters to pass from NS world to
* S world
*/
u32 omap4_secure_dispatcher(u32 app_id, u32 flags, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4)
{
u32 ret;
unsigned long iflags;
u32 pub2sec_args[5] = {0, 0, 0, 0, 0};
/*dprintk(KERN_INFO "omap4_secure_dispatcher: "
"app_id=0x%08x, flags=0x%08x, nargs=%u\n",
app_id, flags, nargs);*/
/*if (nargs != 0)
dprintk(KERN_INFO
"omap4_secure_dispatcher: args=%08x, %08x, %08x, %08x\n",
arg1, arg2, arg3, arg4);*/
pub2sec_args[0] = nargs;
pub2sec_args[1] = arg1;
pub2sec_args[2] = arg2;
pub2sec_args[3] = arg3;
pub2sec_args[4] = arg4;
/* Make sure parameters are visible to the secure world */
dmac_flush_range((void *)pub2sec_args,
(void *)(((u32)(pub2sec_args)) + 5*sizeof(u32)));
outer_clean_range(__pa(pub2sec_args),
__pa(pub2sec_args) + 5*sizeof(u32));
wmb();
/*
* Put L4 Secure clock domain to SW_WKUP so that modules are accessible
*/
tf_l4sec_clkdm_wakeup(false);
local_irq_save(iflags);
#ifdef DEBUG
BUG_ON((read_mpidr() & 0x00000003) != 0);
#endif
/* proc_id is always 0 */
ret = schedule_secure_world(app_id, 0, flags, __pa(pub2sec_args));
local_irq_restore(iflags);
/* Restore the HW_SUP on L4 Sec clock domain so hardware can idle */
tf_l4sec_clkdm_allow_idle(false);
/*dprintk(KERN_INFO "omap4_secure_dispatcher()\n");*/
return ret;
}