static inline uint32_t kpled_read(uint32_t reg)
{
return sci_adi_read(reg);
}
/* A-Die regs ops */
static uint32_t a_read_reg(uint32_t addr)
{
return sci_adi_read(addr);
}
void print_hard_irq_inloop(int ret)
{
unsigned int i, j, val;
unsigned int ana_sts;
unsigned int gpio_irq[GPIO_GROUP_NUM];
if(sprd_irqs_sts[0] != 0)
printk("%c#:INTC0: %08x\n", ret?'S':'F', sprd_irqs_sts[0]);
if(sprd_irqs_sts[1] != 0)
printk("%c#:INTC0 FIQ: %08x\n", ret?'S':'F', sprd_irqs_sts[1]);
if(sprd_irqs_sts[0]&IRQ_EIC){
printk("wake up by eic\n");
}
if(sprd_irqs_sts[0]&IRQ_BUSMON){
printk("wake up by busmoniter\n");
}
if(sprd_irqs_sts[0]&IRQ_WDG){
printk("wake up by ca7_wdg or ap_wdg\n");
}
if(sprd_irqs_sts[0]&IRQ_CP2){
printk("wake up by cp2\n");
}
if(sprd_irqs_sts[0]&IRQ_CP1){
printk("wake up by cp1\n");
}
if(sprd_irqs_sts[0]&IRQ_CP0){
printk("wake up by cp0\n");
}
if(sprd_irqs_sts[0]&IRQ_GPU){
printk("wake up by gpu\n");
}
if(sprd_irqs_sts[0]&IRQ_MM){
printk("wake up by mm\n");
}
if(sprd_irqs_sts[0]&IRQ_4){
if(sprd_hard_irq[34])
printk("wake up by i2c\n");
if(sprd_hard_irq[20])
printk("wake up by audio\n");
if(sprd_hard_irq[27])
printk("wake up by fm\n");
if(sprd_hard_irq[25]){
printk("wake up by adi\n");
}
if(sprd_hard_irq[38]){
printk("wake up by ana ");
ana_sts = sci_adi_read(ANA_REG_INT_RAW_STATUS);
if(ana_sts & BIT(0))
printk("adc\n");
if(ana_sts & BIT(1)){
printk("gpio\n");
printk("gpio 0 ~ 16 0x%08x\n", sci_adi_read(SPRD_MISC_BASE + 0x0480 + 0x1c));
printk("gpio 17 ~ 31 0x%08x\n", sci_adi_read(SPRD_MISC_BASE + 0x0480 + 0x40 + 0x1c));
}
if(ana_sts & BIT(2))
printk("rtc\n");
if(ana_sts & BIT(3))
printk("wdg\n");
if(ana_sts & BIT(4))
printk("fgu\n");
if(ana_sts & BIT(5)){
printk("eic\n");
printk("ana eic 0x%08x\n", sci_adi_read(ANA_EIC_BASE + 0x1c));
}
if(ana_sts & BIT(6))
printk("aud head button\n");
if(ana_sts & BIT(7))
printk("aud protect\n");
if(ana_sts & BIT(8))
printk("thermal\n");
if(ana_sts & BIT(10))
printk("dcdc otp\n");
printk("ANA INT 0x%08x\n", ana_sts);
}
if(sprd_hard_irq[36])
printk("wake up by kpd\n");
if(sprd_hard_irq[35]){
printk("wake up by gpio\n");
}
}
if(sprd_irqs_sts[0]&IRQ_3){
if(sprd_hard_irq[23])
printk("wake up by vbc_ad01\n");
if(sprd_hard_irq[24])
printk("wake up by vbc_ad23\n");
if(sprd_hard_irq[22])
printk("wake up by vbc_da\n");
if(sprd_hard_irq[21])
printk("wake up by afifi_error\n");
}
if(sprd_irqs_sts[0]&IRQ_2){
if(sprd_hard_irq[29]){
printk("wake up by ap_tmr0\n");
}
if(sprd_hard_irq[118]){
printk("wake up by ap_tmr1\n");
}
if(sprd_hard_irq[119]){
printk("wake up by ap_tmr2\n");
}
if(sprd_hard_irq[120]){
printk("wake up by ap_tmr3\n");
}
if(sprd_hard_irq[121]){
printk("wake up by ap_tmr4\n");
}
if(sprd_hard_irq[31]){
printk("wake up by ap_syst\n");
}
if(sprd_hard_irq[30]){
printk("wake up by aon_syst\n");
}
if(sprd_hard_irq[28]){
printk("wake up by aon_tmr\n");
}
}
if (sprd_hard_irq[35]) {
for(i=0; i<(GPIO_GROUP_NUM/2); i++){
j = 2*i;
gpio_irq[j]= __raw_readl(SPRD_GPIO_BASE + 0x100*i + REG_GPIO_MIS);
gpio_irq[j+1]= __raw_readl(SPRD_GPIO_BASE + 0x100*i + 0x80 + REG_GPIO_MIS);
// printk("gpio_irq[%d]:0x%x, gpio_irq[%d]:0x%x \n", j, gpio_irq[j], j+1, gpio_irq[j+1]);
}
for(i=0; i<GPIO_GROUP_NUM; i++){
if(gpio_irq[i] != 0){
val = gpio_irq[i];
while(val){
j = __ffs(val);
printk("irq from gpio%d\n", j + 16*i);
val &= ~(1<<j);
}
}
}
}
}
static void print_debug_info(void)
{
unsigned int ahb_eb, apb_eb0, cp_slp_status0, cp_slp_status1, ldo_pd_ctrl,
ap_apb_eb, apb_pwrstatus0, apb_pwrstatus1, apb_pwrstatus2,
apb_pwrstatus3, mpll_cfg, dpll_cfg, emc_clk_cfg,
apb_slp_status, ap_sys_auto_sleep_cfg;
#if defined(CONFIG_ARCH_SCX15)
unsigned int ldo_dcdc_pd_ctrl;
#endif
ahb_eb = sci_glb_read(REG_AP_AHB_AHB_EB, -1UL);
ap_sys_auto_sleep_cfg = sci_glb_read(REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG, -1UL);
ap_apb_eb = sci_glb_read(REG_AP_APB_APB_EB, -1UL);
apb_eb0 = sci_glb_read(REG_AON_APB_APB_EB0, -1UL);
cp_slp_status0 = sci_glb_read(REG_PMU_APB_CP_SLP_STATUS_DBG0, -1UL);
cp_slp_status1 = sci_glb_read(REG_PMU_APB_CP_SLP_STATUS_DBG1, -1UL);
apb_pwrstatus0 = sci_glb_read(REG_PMU_APB_PWR_STATUS0_DBG, -1UL);
apb_pwrstatus1 = sci_glb_read(REG_PMU_APB_PWR_STATUS1_DBG, -1UL);
apb_pwrstatus2 = sci_glb_read(REG_PMU_APB_PWR_STATUS2_DBG, -1UL);
apb_pwrstatus3 = sci_glb_read(REG_PMU_APB_PWR_STATUS3_DBG, -1UL);
apb_slp_status = __raw_readl(REG_PMU_APB_SLEEP_STATUS);
mpll_cfg = sci_glb_read(REG_AON_APB_MPLL_CFG, -1UL);
dpll_cfg = sci_glb_read(REG_AON_APB_DPLL_CFG, -1UL);
emc_clk_cfg = sci_glb_read(REG_AON_CLK_EMC_CFG, -1UL);
ldo_pd_ctrl = sci_adi_read(ANA_REG_GLB_LDO_PD_CTRL);
#if defined(CONFIG_ARCH_SCX15)
ldo_dcdc_pd_ctrl = sci_adi_read(ANA_REG_GLB_LDO_DCDC_PD);
#endif
printk("###---- REG_AP_AHB_AHB_EB : 0x%08x\n", ahb_eb);
printk("###---- REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG : 0x%08x\n", ap_sys_auto_sleep_cfg);
printk("###---- REG_AP_APB_APB_EB : 0x%08x\n", ap_apb_eb);
printk("###---- REG_AON_APB_APB_EB0 : 0x%08x\n", apb_eb0);
printk("###---- REG_PMU_APB_CP_SLP_STATUS_DBG0 : 0x%08x\n", cp_slp_status0);
printk("###---- REG_PMU_APB_CP_SLP_STATUS_DBG1 : 0x%08x\n", cp_slp_status1);
printk("###---- REG_PMU_APB_PWR_STATUS0_DBG : 0x%08x\n", apb_pwrstatus0);
printk("###---- REG_PMU_APB_PWR_STATUS1_DBG : 0x%08x\n", apb_pwrstatus1);
printk("###---- REG_PMU_APB_PWR_STATUS2_DBG : 0x%08x\n", apb_pwrstatus2);
printk("###---- REG_PMU_APB_PWR_STATUS3_DBG : 0x%08x\n", apb_pwrstatus3);
printk("###---- REG_PMU_APB_SLEEP_STATUS : 0x%08x\n", apb_slp_status);
printk("###---- REG_AON_APB_MPLL_CFG : 0x%08x\n", mpll_cfg);
printk("###---- REG_AON_APB_DPLL_CFG : 0x%08x\n", dpll_cfg);
printk("###---- REG_AON_CLK_EMC_CFG : 0x%08x\n", emc_clk_cfg);
printk("###---- ANA_REG_GLB_LDO_PD_CTRL : 0x%08x\n", ldo_pd_ctrl);
#if defined(CONFIG_ARCH_SCX15)
printk("###---- ANA_REG_GLB_LDO_DCDC_PD_CTRL : 0x%08x\n", ldo_dcdc_pd_ctrl);
#endif
if (apb_eb0 & BIT_GPU_EB)
printk("###---- BIT_GPU_EB still set ----###\n");
if (apb_eb0 & BIT_MM_EB)
printk("###---- BIT_MM_EB still set ----###\n");
if (apb_eb0 & BIT_CA7_DAP_EB)
printk("###---- BIT_CA7_DAP_EB still set ----###\n");
if (ahb_eb & BIT_GSP_EB)
printk("###---- BIT_GSP_EB still set ----###\n");
if (ahb_eb & BIT_DISPC1_EB)
printk("###---- BIT_DISPC1_EB still set ----###\n");
if (ahb_eb & BIT_DISPC0_EB)
printk("###---- BIT_DISPC0_EB still set ----###\n");
if (ahb_eb & BIT_SDIO0_EB)
printk("###---- SDIO0_EB still set ----###\n");
if (ahb_eb & BIT_SDIO1_EB)
printk("###---- SDIO1_EB still set ----###\n");
if (ahb_eb & BIT_SDIO2_EB)
printk("###---- BIT_SDIO2_EB still set ----###\n");
if (ahb_eb & BIT_USB_EB)
printk("###---- BIT_USB_EB still set ----###\n");
if (ahb_eb & BIT_DMA_EB)
printk("###---- BIT_DMA_EB still set ----###\n");
if (ahb_eb & BIT_NFC_EB)
printk("###---- BIT_NFC_EB still set ----###\n");
if (ahb_eb & BIT_EMMC_EB)
printk("###---- BIT_EMMC_EB still set ----###\n");
#if defined(CONFIG_ARCH_SCX15)
if (ahb_eb & BIT_ZIPDEC_EB)
printk("###---- BIT_ZIPDEC_EB still set ----###\n");
if (ahb_eb & BIT_ZIPENC_EB)
printk("###---- BIT_ZIPENC_EB still set ----###\n");
if (ahb_eb & BIT_NANDC_ECC_EB)
printk("###---- BIT_NANDC_ECC_EB still set ----###\n");
if (ahb_eb & BIT_NANDC_2X_EB)
printk("###---- BIT_NANDC_2X_EB still set ----###\n");
if (ahb_eb & BIT_NANDC_EB)
printk("###---- BIT_NANDC_EB still set ----###\n");
#endif
/*A-die*/
if (!(ldo_pd_ctrl & BIT_DCDC_WPA_PD))
printk("###---- BIT_DCDC_WPA_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CLSG_PD))
printk("###---- BIT_LDO_CLSG_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_USB_PD))
printk("###---- BIT_LDO_USB_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CAMMOT_PD))
printk("###---- BIT_LDO_CAMMOT_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CAMIO_PD))
printk("###---- BIT_LDO_CAMIO_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CAMD_PD))
printk("###---- BIT_LDO_CAMD_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CAMA_PD))
printk("###---- BIT_LDO_CAMA_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_SIM2_PD))
printk("###---- BIT_LDO_SIM2_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_SIM1_PD))
printk("###---- BIT_LDO_SIM1_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_SIM0_PD))
printk("###---- BIT_LDO_SIM0_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_SD_PD))
printk("###---- BIT_LDO_SD_PD power on! ----###\n");
#if defined(CONFIG_ARCH_SCX15)
if (!(ldo_dcdc_pd_ctrl & BIT_BG_PD))
printk("###---- BIT_BG_PD power on! ----###\n");
if (!(ldo_dcdc_pd_ctrl & BIT_LDO_CON_PD))
printk("###---- BIT_LDO_CON_PD power on! ----###\n");
if (!(ldo_dcdc_pd_ctrl & BIT_LDO_DCXO_PD))
printk("###---- BIT_LDO_DCXO_PD power on! ----###\n");
if (!(ldo_dcdc_pd_ctrl & BIT_LDO_EMMCIO_PD))
printk("###---- BIT_LDO_EMMCIO_PD power on! ----###\n");
if (!(ldo_dcdc_pd_ctrl & BIT_LDO_EMMCCORE_PD))
printk("###---- BIT_LDO_EMMCCORE_PD power on! ----###\n");
#endif
#if defined(CONFIG_ARCH_SCX15)
if (ap_apb_eb & BIT_UART4_EB)
printk("###---- BIT_UART4_EB set! ----###\n");
if (ap_apb_eb & BIT_UART3_EB)
printk("###---- BIT_UART3_EB set! ----###\n");
if (ap_apb_eb & BIT_UART2_EB)
printk("###---- BIT_UART2_EB set! ----###\n");
if (ap_apb_eb & BIT_UART1_EB)
printk("###---- BIT_UART1_EB set! ----###\n");
if (ap_apb_eb & BIT_UART0_EB)
printk("###---- BIT_UART0_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C4_EB)
printk("###---- BIT_I2C4_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C3_EB)
printk("###---- BIT_I2C3_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C2_EB)
printk("###---- BIT_I2C2_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C1_EB)
printk("###---- BIT_I2C1_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C0_EB)
printk("###---- BIT_I2C0_EB set! ----###\n");
if (ap_apb_eb & BIT_IIS3_EB)
printk("###---- BIT_IIS3_EB set! ----###\n");
if (ap_apb_eb & BIT_IIS2_EB)
printk("###---- BIT_IIS2_EB set! ----###\n");
if (ap_apb_eb & BIT_IIS1_EB)
printk("###---- BIT_IIS1_EB set! ----###\n");
if (ap_apb_eb & BIT_IIS0_EB)
printk("###---- BIT_IIS0_EB set! ----###\n");
#endif
}
static inline uint32_t vibrator_read(uint32_t reg)
{
return sci_adi_read(reg);
}
static inline unsigned get_day(void)
{
return sci_adi_read(ANA_RTC_DAY_CNT) & RTC_DAY_MASK;
}
static inline unsigned get_hour(void)
{
return sci_adi_read(ANA_RTC_HOUR_CNT) & RTC_HOUR_MASK;
}
static inline unsigned get_min(void)
{
return sci_adi_read(ANA_RTC_MIN_CNT) & RTC_MIN_MASK;
}
static inline unsigned get_sec(void)
{
return sci_adi_read(ANA_RTC_SEC_CNT) & RTC_SEC_MASK;
}
