static int32_t isp_module_rst(struct isp_k_file *file)
{
int32_t ret = 0;
struct isp_k_private *isp_private = NULL;
if (!file) {
printk("isp_module_rst: file is null error.\n");
return -1;
}
isp_private = file->isp_private;
if (!isp_private) {
printk("isp_module_rst: isp_private is null error.\n");
return -1;
}
if (0x00 != atomic_read(&isp_private->users)) {
ret = isp_axi_bus_waiting();
isp_clr_int();
sci_glb_set(ISP_MODULE_RESET, ISP_RST_LOG_BIT);
sci_glb_set(ISP_MODULE_RESET, ISP_RST_CFG_BIT);
sci_glb_set(ISP_MODULE_RESET, ISP_RST_LOG_BIT);
sci_glb_set(ISP_MODULE_RESET, ISP_RST_CFG_BIT);
sci_glb_set(ISP_MODULE_RESET, ISP_RST_LOG_BIT);
sci_glb_set(ISP_MODULE_RESET, ISP_RST_CFG_BIT);
sci_glb_clr(ISP_MODULE_RESET, ISP_RST_CFG_BIT);
sci_glb_clr(ISP_MODULE_RESET, ISP_RST_LOG_BIT);
}
return ret;
}
void dsi_disable(void)
{
sci_glb_set(REG_AON_APB_PWR_CTRL, BIT_MIPI_DSI_PS_PD_S);
sci_glb_set(REG_AON_APB_PWR_CTRL, BIT_MIPI_DSI_PS_PD_L);
sci_glb_clr(REG_AP_AHB_MISC_CKG_EN, BIT_DPHY_REF_CKG_EN);
sci_glb_clr(REG_AP_AHB_MISC_CKG_EN, BIT_DPHY_CFG_CKG_EN);
sci_glb_clr(DSI_REG_EB, DSI_BIT_EB);
}
void dsi_enable(void)
{
sci_glb_clr(REG_AON_APB_PWR_CTRL, BIT_MIPI_DSI_PS_PD_S);
sci_glb_clr(REG_AON_APB_PWR_CTRL, BIT_MIPI_DSI_PS_PD_L);
sci_glb_set(REG_AP_AHB_MISC_CKG_EN, BIT_DPHY_REF_CKG_EN);
sci_glb_set(REG_AP_AHB_MISC_CKG_EN, BIT_DPHY_CFG_CKG_EN);
pr_info("sprdfb: dsi_enable %08x\n", REG_AP_AHB_MISC_CKG_EN);
sci_glb_set(DSI_REG_EB, DSI_BIT_EB);
}
void sprd_usb_phy_rst(void)
{
sci_glb_set(USB_GUSBCFG_REG, BIT(3));/*usc2s8c SPRD phy width:16 bit*/
sci_glb_clr(AP_TOP_USB_PHY_RST, BIT(0));/*for SPRD phy utmi_PORN*/
sci_glb_set(REG_AP_AHB_AHB_RST, BIT(7));/*for SPRD phy utmi_rst*/
mdelay(5);
sci_glb_set(AP_TOP_USB_PHY_RST, BIT(0));
sci_glb_clr(REG_AP_AHB_AHB_RST, BIT(7));
}
int32_t dcam_reset(enum dcam_rst_mode reset_mode)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
uint32_t time_out = 0;
if (atomic_read(&s_dcam_users)) {
/* firstly, stop AXI writing */
REG_OWR(DCAM_BURST_GAP, BIT_18);
}
/* then wait for AHB busy cleared */
while (++time_out < DCAM_AXI_STOP_TIMEOUT) {
if (0 == (REG_RD(DCAM_AHBM_STS) & BIT_0))
break;
}
if (time_out >= DCAM_AXI_STOP_TIMEOUT)
return DCAM_RTN_TIMEOUT;
/* do reset action */
switch (reset_mode) {
case DCAM_RST_PATH1:
sci_glb_set(DCAM_RST, PATH1_RST_BIT);
sci_glb_set(DCAM_RST, CCIR_RST_BIT);
sci_glb_clr(DCAM_RST, PATH1_RST_BIT);
sci_glb_clr(DCAM_RST, CCIR_RST_BIT);
/*
REG_OWR(DCAM_RST, DCAM_MOD_RST_BIT);
REG_OWR(DCAM_RST, CCIR_RST_BIT);
REG_AWR(DCAM_RST, ~DCAM_MOD_RST_BIT);
REG_AWR(DCAM_RST, ~CCIR_RST_BIT);
*/
DCAM_TRACE("DCAM DRV: reset path1 \n");
break;
case DCAM_RST_PATH2:
sci_glb_set(DCAM_RST, PATH2_RST_BIT);
sci_glb_clr(DCAM_RST, PATH2_RST_BIT);
DCAM_TRACE("DCAM DRV: reset path2 \n");
break;
case DCAM_RST_ALL:
sci_glb_set(DCAM_RST, DCAM_MOD_RST_BIT);
sci_glb_set(DCAM_RST, CCIR_RST_BIT);
sci_glb_clr(DCAM_RST, DCAM_MOD_RST_BIT);
sci_glb_clr(DCAM_RST, CCIR_RST_BIT);
DCAM_TRACE("DCAM DRV: reset all \n");
break;
default:
rtn = DCAM_RTN_PARA_ERR;
break;
}
if (atomic_read(&s_dcam_users)) {
/* the end, enable AXI writing */
REG_AWR(DCAM_BURST_GAP, ~BIT_18);
}
return -rtn;
}
static void usb_enable_module(int en)
{
if (en){
sci_glb_clr(REG_AON_APB_PWR_CTRL,BIT(0));
sci_glb_set(REG_AP_AHB_AHB_EB,BIT_USB_EB);
}else {
sci_glb_set(REG_AON_APB_PWR_CTRL,BIT(0));
sci_glb_clr(REG_AP_AHB_AHB_EB,BIT_USB_EB);
}
}
static void gps_reg_init(void)
{
#ifdef CONFIG_ARCH_SCX30G
/*GPS Clock Select to CLK_SINE0*/
sci_glb_clr(SPRD_GPS_CLK_SEL,BIT_3);
/*Disable 26M Clock Gating*/
sci_glb_clr(SPRD_GPS_CLK_AUTO_GATING,BIT_0);
#endif
}
int __init __clock_init_early(void)
{
pr_info("ahb ctl0 %08x, ctl2 %08x glb aon apb0 %08x aon apb1 %08x clk_en %08x\n",
sci_glb_raw_read(REG_AP_AHB_AHB_EB),
sci_glb_raw_read(REG_AP_AHB_AHB_RST),
sci_glb_raw_read(REG_AON_APB_APB_EB0),
sci_glb_raw_read(REG_AON_APB_APB_EB1),
sci_glb_raw_read(REG_AON_CLK_PUB_AHB_CFG));
sci_glb_clr(REG_AP_AHB_AHB_EB,
BIT_BUSMON2_EB |
BIT_BUSMON1_EB |
BIT_BUSMON0_EB |
BIT_GPS_EB |
BIT_DRM_EB |
BIT_NFC_EB |
0);
sci_glb_clr(REG_AP_APB_APB_EB,
BIT_INTC3_EB |
BIT_INTC2_EB |
BIT_INTC1_EB |
BIT_IIS1_EB |
BIT_UART2_EB |
BIT_UART0_EB |
BIT_SPI1_EB |
BIT_SPI0_EB |
BIT_IIS0_EB |
BIT_I2C0_EB |
BIT_SPI2_EB |
BIT_UART3_EB |
0);
sci_glb_clr(REG_AON_APB_APB_RTC_EB,
BIT_KPD_RTC_EB |
BIT_KPD_EB |
BIT_EFUSE_EB |
0);
sci_glb_clr(REG_AON_APB_APB_EB0,
BIT_AUDIF_EB |
BIT_VBC_EB |
BIT_PWM3_EB |
BIT_PWM1_EB |
0);
sci_glb_clr(REG_AON_APB_APB_EB1,
BIT_AUX1_EB |
BIT_AUX0_EB |
0);
pr_debug("sc clock module early init ok\n");
return 0;
}
static __devinit void __keypad_enable(void)
{
sci_glb_set(REG_GLB_SOFT_RST, BIT_KPD_RST);
mdelay(2);
sci_glb_clr(REG_GLB_SOFT_RST, BIT_KPD_RST);
sci_glb_set(REG_GLB_GEN0, BIT_KPD_EB | BIT_RTC_KPD_EB);
}
/* lcdc soft reset */
static void lcdc_reset(void)
{
#define REG_AHB_SOFT_RST (AHB_SOFT_RST + SPRD_AHB_BASE)
sci_glb_set(REG_AHB_SOFT_RST, (1<<LCDC_SOFT_RST));
udelay(10);
sci_glb_clr(REG_AHB_SOFT_RST, (1<<LCDC_SOFT_RST) );
}
int32_t dcam_module_en(void)
{
int ret = 0;
DCAM_TRACE("DCAM DRV: dcam_module_en: %d \n", s_dcam_users.counter);
if (atomic_inc_return(&s_dcam_users) == 1) {
ret = dcam_set_clk(DCA_CLK_256M);
/*REG_OWR(DCAM_EB, DCAM_EB_BIT);*/
sci_glb_set(DCAM_RST, DCAM_MOD_RST_BIT);
sci_glb_set(DCAM_RST, CCIR_RST_BIT);
sci_glb_clr(DCAM_RST, DCAM_MOD_RST_BIT);
sci_glb_clr(DCAM_RST, CCIR_RST_BIT);
}
return ret;
}
static void __keypad_enable(void)
{
sci_glb_set(REG_AON_APB_APB_RST0, BIT_KPD_SOFT_RST);
mdelay(2);
sci_glb_clr(REG_AON_APB_APB_RST0, BIT_KPD_SOFT_RST);
sci_glb_set(REG_AON_APB_APB_EB0, BIT_KPD_EB);
sci_glb_set(REG_AON_APB_APB_RTC_EB, BIT_KPD_RTC_EB);
}
static void efuse_reset(void)
{
/* should enable module before soft reset efuse */
WARN_ON(!sci_glb_read(REG_AON_APB_APB_EB0, BIT_EFUSE_EB));
sci_glb_set(REG_AON_APB_APB_RST0, BIT_EFUSE_SOFT_RST);
udelay(5);
sci_glb_clr(REG_AON_APB_APB_RST0, BIT_EFUSE_SOFT_RST);
}
int sprd_charger_is_adapter(struct sprd_battery_data *data)
{
uint32_t ret;
volatile uint32_t i;
unsigned long irq_flag = 0;
mdelay(300);
gpio_request(USB_DM_GPIO, "sprd_charge");
gpio_request(USB_DP_GPIO, "sprd_charge");
gpio_direction_input(USB_DM_GPIO);
gpio_direction_input(USB_DP_GPIO);
udc_enable();
udc_phy_down();
local_irq_save(irq_flag);
sci_glb_clr(REG_AHB_USB_PHY_CTRL, (BIT_DMPULLDOWN | BIT_DPPULLDOWN));
/* Identify USB charger */
sci_glb_set(REG_AHB_USB_PHY_CTRL, BIT_DMPULLUP);
mdelay(10);
ret = gpio_get_value(USB_DM_GPIO);
sci_glb_clr(REG_AHB_USB_PHY_CTRL, (BIT_DMPULLUP));
#if 0
/* normal charger */
if (ret) {
/* Identify standard adapter */
sci_glb_set(REG_AHB_USB_PHY_CTRL, BIT_DMPULLDOWN);
for (i = 0; i < 1000; i++) {;
}
if (gpio_get_value(USB_DM_GPIO)
== gpio_get_value(USB_DP_GPIO)) {
ret = 1; /* adapter */
} else {
ret = 1; /* non standard adapter */
}
sci_glb_clr(REG_AHB_USB_PHY_CTRL, (BIT_DMPULLDOWN));
}
#endif
local_irq_restore(irq_flag);
udc_disable();
gpio_free(USB_DM_GPIO);
gpio_free(USB_DP_GPIO);
return ret;
}
void usb_phy_ahb_rst(void)
{
#if defined(CONFIG_ARCH_SCX35)
#if defined(CONFIG_ARCH_SCX35L)
sci_glb_set(REG_AP_AHB_AHB_RST,BIT(6));
mdelay(3);
sci_glb_clr(REG_AP_AHB_AHB_RST,BIT(6));
mdelay(3);
sci_glb_set(REG_AP_AHB_OTG_PHY_CTRL,BIT(9));
pr_info("Usb_hw.c: [%s]usb phy tune : 0x%x\n", __FUNCTION__, tune_from_uboot);
#else
sci_glb_set(REG_AP_AHB_AHB_RST,BIT(7));
mdelay(3);
sci_glb_clr(REG_AP_AHB_AHB_RST,BIT(7));
mdelay(3);
#endif
#endif
}
void usb_phy_ahb_rst(void)
{
#if defined(CONFIG_ARCH_SCX35)
sci_glb_set(REG_AP_AHB_AHB_RST,BIT(7));
mdelay(3);
sci_glb_clr(REG_AP_AHB_AHB_RST,BIT(7));
mdelay(3);
#endif
}
void enable_cpuidle(int enable)
{
#if defined(CONFIG_LOCAL_TIMERS)
if(enable)
sci_glb_set(REG_AHB_AHB_CTL1, BIT_ARM_AUTO_GATE_EN);
else
sci_glb_clr(REG_AHB_AHB_CTL1, BIT_ARM_AUTO_GATE_EN);
#endif
}
static void dsi_reset(void)
{
pr_debug("[DISP] sprdfb:DSI_AHB_SOFT_RST:%x,BIT_DSI_SOFT_RST:%lx\n",DSI_AHB_SOFT_RST,BIT_DSI_SOFT_RST);
pr_debug("[DISP] sprdfb:DSI_AHB_SOFT_RST:%x \n",dispc_glb_read(DSI_AHB_SOFT_RST));
sci_glb_set(DSI_AHB_SOFT_RST, BIT_DSI_SOFT_RST);
pr_debug("[DISP] sprdfb:DSI_AHB_SOFT_RST:%x \n",dispc_glb_read(DSI_AHB_SOFT_RST));
udelay(10);
sci_glb_clr(DSI_AHB_SOFT_RST, BIT_DSI_SOFT_RST);
pr_debug("[DISP] sprdfb:DSI_AHB_SOFT_RST:%x \n",dispc_glb_read(DSI_AHB_SOFT_RST));
}
static void emc_earlysuspend_late_resume(struct early_suspend *h)
{
//printk("emc_earlysuspend_late_resume\n");
//hw_local_irq_disable();
sci_glb_clr(REG_AHB_AHB_CTL1, BIT_EMC_AUTO_GATE_EN);
cp_do_change_emc_freq(EMC_SWITCH_TO_DLL_ENABLE_MODE, 0);
close_cp();
//hw_local_irq_enable();
//printk("emc_earlysuspend_late_resume ---");
}
int32_t dcam_module_dis(void)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
DCAM_TRACE("DCAM DRV: dcam_module_dis: %d \n", s_dcam_users.counter);
if (atomic_dec_return(&s_dcam_users) == 0) {
sci_glb_clr(DCAM_EB, DCAM_EB_BIT);
dcam_set_clk(DCAM_CLK_NONE);
}
return -rtn;
}
static void __init __dma_reg_init(void)
{
int i = 0x100;
sci_glb_set(REG_AP_AHB_AHB_RST, 0x1 << 8);
while (i--) ;
sci_glb_clr(REG_AP_AHB_AHB_RST, 0x1 << 8);
__raw_writel(0x0, DMA_FRAG_WAIT);
}
int __init sci_adi_init(void)
{
/* enable adi in global regs */
sci_glb_set(REG_GLB_GEN0,BIT_ADI_EB);
/* reset adi */
sci_glb_set(REG_GLB_SOFT_RST,BIT_ADI_RST);
udelay(2);
sci_glb_clr(REG_GLB_SOFT_RST,BIT_ADI_RST);
__sci_adi_init();
return 0;
}
//bxd add for slck enable
TCgReturnCode CGCoreSclkEnable(int enable)
{
TCgReturnCode rc = ECgOk;
if(1 == enable)
{
sci_glb_set(CG_DRIVER_SCLK_VA,BIT_12);
}
else if(0 == enable)
{
sci_glb_clr(CG_DRIVER_SCLK_VA,BIT_12);
}
return rc;
}
static void usb_startup(void)
{
usb_ldo_switch(1);
mdelay(10);
usb_enable_module(1);
mdelay(2);
#if (defined(CONFIG_ARCH_SCX35)||defined(CONFIG_ARCH_SCX35L64)||defined(CONFIG_ARCH_SCX35LT8))
#if defined(CONFIG_ARCH_SCX30G)
#if defined(CONFIG_ARCH_SCX20)
sci_glb_set(REG_AP_AHB_AHB_RST, BIT(5)|BIT(6));
mdelay(5);
sci_glb_clr(REG_AP_AHB_AHB_RST, BIT(5)|BIT(6));
sprd_usb_phy_rst();
#else
sci_glb_set(REG_AP_AHB_AHB_RST,BIT(5)|BIT(6)|BIT(7));
mdelay(5);
sci_glb_clr(REG_AP_AHB_AHB_RST,BIT(5)|BIT(6)|BIT(7));
#endif
#else
sci_glb_set(REG_AP_AHB_AHB_RST,BIT_OTG_SOFT_RST|BIT_OTG_UTMI_SOFT_RST|BIT_OTG_PHY_SOFT_RST);
mdelay(5);
sci_glb_clr(REG_AP_AHB_AHB_RST,BIT_OTG_SOFT_RST|BIT_OTG_UTMI_SOFT_RST|BIT_OTG_PHY_SOFT_RST);
sci_glb_set(REG_AP_AHB_AHB_EB,BIT_USB_EB);
#endif
#else
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT_USB_S_HBIGEIDIAN|BIT_USB_M_HBIGENDIAN,REG_AHB_AHB_CTL3);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT_CLK_USB_REF_EN,REG_AHB_AHB_CTL3);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT_USBD_UTMI_SOFT_RST|BIT_USBPHY_SOFT_RST ,REG_AHB_SOFT_RST);
mdelay(5);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT_USBD_UTMI_SOFT_RST|BIT_USBPHY_SOFT_RST,REG_AHB_SOFT_RST);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT_USBD_EB,REG_AHB_AHB_CTL0);
#endif
mdelay(3);
}
void __efuse_power_off(void)
{
u32 cfg0 = __raw_readl((void *)REG_EFUSE_CFG0);
if (cfg0 & BIT_EFS_VDDQ_K1_ON) {
cfg0 &= ~BIT_EFS_VDDQ_K1_ON;
__raw_writel(cfg0, (void *)REG_EFUSE_CFG0);
msleep(1);
}
cfg0 |= BIT_EFS_VDDQ_K2_ON;
cfg0 &= ~BIT_EFS_VDD_ON;
__raw_writel(cfg0, (void *)REG_EFUSE_CFG0);
msleep(1);
sci_glb_clr(REG_AON_APB_APB_EB0, BIT_EFUSE_EB);
}
void __init sci_enable_timer_early(void)
{
/* enable timer & syscnt in global regs */
int i = 0, j = 0;
sci_glb_set(REG_AON_APB_APB_EB0,
BIT_AON_TMR_EB | BIT_AP_SYST_EB | BIT_AP_TMR0_EB);
#if defined CONFIG_LOCAL_TIMERS && !defined CONFIG_HAVE_ARM_ARCH_TIMER
sci_glb_set(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB);
for (i = 0; i < 4; i++) {
#else
sci_glb_clr(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB);
for (i = 0; i < 2; i++) {
#endif
for (j = 0; j < 3; j++) {
__gptimer_ctl(i, j, TIMER_DISABLE, 0);
__raw_writel(TIMER_INT_CLR, TIMER_INT(i, j));
}
}
#if defined(CONFIG_ARCH_SCX30G) || defined(CONFIG_ARCH_SCX35L)
/*timer1 fixed 32768 clk */
sched_clock_source_freq = 32768;
#else /*timer2 clk source is from apb clk */
val = sci_glb_read(REG_AON_CLK_AON_APB_CFG, -1) & 0x3;
if (val == 0x1)
sched_clock_source_freq = 76800000;
else if (val == 0x2)
sched_clock_source_freq = 96000000;
else if (val == 0x3)
sched_clock_source_freq = 128000000;
else
sched_clock_source_freq = 26000000; /*default setting */
#endif
gptimer_clock_source_freq = sched_clock_source_freq;
#if !defined (CONFIG_HAVE_ARM_ARCH_TIMER)
__sched_clock_init(sched_clock_source_freq);
#endif
}
u32 get_sys_cnt(void)
{
u32 val = 0;
val = __raw_readl(SYSCNT_SHADOW_CNT);
return val;
}
static void sdhci_module_init(struct sdhci_host* host)
{
struct sprd_host_platdata *host_pdata;
host_pdata = sdhci_get_platdata(host);
sci_glb_set(REG_AP_AHB_AHB_EB, host_pdata->enb_bit);
sdhci_sdclk_enable(host, 0);
sci_glb_set(REG_AP_AHB_AHB_RST, host_pdata->rst_bit);
udelay(200);
sci_glb_clr(REG_AP_AHB_AHB_RST, host_pdata->rst_bit);
sdhci_sprd_set_base_clock(host);
host->ops->set_clock(host, true);
}
static void usb_startup(void)
{
usb_ldo_switch(1);
mdelay(10);
usb_enable_module(1);
mdelay(2);
#if defined(CONFIG_ARCH_SCX35)
sci_glb_set(REG_AP_AHB_AHB_RST,BIT(5)|BIT(6)|BIT(7));
mdelay(5);
sci_glb_clr(REG_AP_AHB_AHB_RST,BIT(5)|BIT(6)|BIT(7));
#else
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(1)|BIT(2),AHB_CTL3);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(6),AHB_CTL3);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(6)|BIT(7),AHB_SOFT_RST);
mdelay(5);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(6)|BIT(7),AHB_SOFT_RST);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,AHB_CTL0_USBD_EN,AHB_CTL0);
#endif
mdelay(3);
}
static int __init sprd_dma_init(void)
{
int ret;
/* enable DMAC */
sci_glb_set(REG_AHB_AHB_CTL0, BIT_DMA_EB);
/* reset the DMAC */
__raw_writel(0, DMA_CHx_EN);
__raw_writel(0, DMA_LINKLIST_EN);
__raw_writel(0, DMA_SOFT_REQ);
__raw_writel(0, DMA_PRI_REG0);
__raw_writel(0, DMA_PRI_REG1);
__raw_writel(0xffffffff, DMA_LISTDONE_INT_CLR);
__raw_writel(0xffffffff, DMA_TRANSF_INT_CLR);
__raw_writel(0xffffffff, DMA_BURST_INT_CLR);
__raw_writel(0, DMA_LISTDONE_INT_EN);
__raw_writel(0, DMA_TRANSF_INT_EN);
__raw_writel(0, DMA_BURST_INT_EN);
/*set hard/soft burst wait time*/
reg_writel(DMA_CFG, 0, DMA_HARD_WAITTIME, 0xff);
reg_writel(DMA_CFG,16, DMA_SOFT_WAITTIME, 0xffff);
/*register dma irq handle*/
ret = request_irq(IRQ_DMA_INT, sprd_dma_irq, 0, "sprd-dma", NULL);
if (ret == 0) {
printk(KERN_INFO "request dma irq ok\n");
} else {
printk(KERN_ERR "request dma irq failed %d\n", ret);
goto request_irq_err;
}
return ret;
request_irq_err:
/* disable DMAC */
sci_glb_clr(REG_AHB_AHB_CTL0, BIT_DMA_EB);
return ret;
}
static void dispc_reset(void)
{
sci_glb_set(REG_AHB_SOFT_RST, (BIT_DISPC_SOFT_RST) );
udelay(10);
sci_glb_clr(REG_AHB_SOFT_RST, (BIT_DISPC_SOFT_RST) );
}
