/* Enable the specified GCLK output on the nominated pin for the selected board. */
static void local_enable_gclk_on_gpio(volatile avr32_pm_t* pm)
{
#if ( BOARD == STK600_RCUC3L0 ) || ( BOARD == UC3C_EK ) || ( BOARD == STK600_RCUC3D )
// Note: for UC3L and UC3C devices, the generic clock configurations are handled
// by the SCIF module.
/* setup generic clock on Osc0, no divisor */
scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_OSC0, AVR32_SCIF_GC_NO_DIV_CLOCK, 0);
/* Now enable the generic clock */
scif_gc_enable(EXAMPLE_GCLK_ID);
#else
/* setup generic clock on Osc0, no divisor */
pm_gc_setup(pm, EXAMPLE_GCLK_ID, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, AVR32_GC_NO_DIV_CLOCK, 0);
/* Now enable the generic clock */
pm_gc_enable(pm, EXAMPLE_GCLK_ID);
#endif
/* Assign a GPIO to generic clock output */
gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
// Note that gclk0_1 is GPIO pin 51 pb19 on AT32UC3A0512 QFP144.
// Note that gclk2 is GPIO pin 30 pa30 on AT32UC3B0256 QFP64.
// Note that gclk1 is GPIO pin 43 pb11 on AT32UC3A3256 QFP144.
// Note that gclk1 is GPIO pin 6 pa06 on AT32UC3L064 pin 10 on QFP48.
// Note that gclk0 is GPIO pin 54 pb22 on AT32UC3C0512C QFP144.
// Note that gclk0 is GPIO pin 9 pa03 on ATUC128D3 QFN64.
}
void demo_init_pwma(void)
{
// Enable the pins driving the LEDs with the PWMA function (functionality E).
gpio_enable_module_pin(LED0_GPIO, LED0_PWM_FUNCTION);
gpio_enable_module_pin(LED1_GPIO, LED1_PWM_FUNCTION);
gpio_enable_module_pin(LED2_GPIO, LED2_PWM_FUNCTION);
gpio_enable_module_pin(LED3_GPIO, LED3_PWM_FUNCTION);
//#
//# Setup and enable the "PWMA and GCLK3 pin" generic clock to 120MHz
//#
// Start the RC120M clock
scif_start_rc120M();
// Setup the generic clock at 120MHz
scif_gc_setup( AVR32_PM_GCLK_PWMA, // The generic clock to setup
SCIF_GCCTRL_RC120M, // The input clock source to use for the generic clock
false, // Disable the generic clock divisor
0); // divfactor = DFLL0freq/gclkfreq
// Enable the generic clock
scif_gc_enable(AVR32_PM_GCLK_PWMA);
//#
//# Enable all the PWMAs to output to all LEDs. LEDs are default turned on by
//# setting PWM duty cycles to 0.
//#
pwma_config_enable(&AVR32_PWMA,PWMA_OUTPUT_FREQUENCY,PWMA_GCLK_FREQUENCY,0);
pwma_set_channels_value(&AVR32_PWMA,LED_PWMA_CHANNELS_MASK,PWMA_DUTY_CYCLE_INIT_VAL);
}
void can_bus_init(int channel, can_stream_config_t config) {
// Setup the generic clock for CAN
scif_gc_setup(AVR32_SCIF_GCLK_CANIF,
CAN_GCLK_SOURCE,
CAN_GCLK_DIV_MODE,
CAN_GCLK_DIV);
// Now enable the generic clock
scif_gc_enable(AVR32_SCIF_GCLK_CANIF);
// Assign GPIO to CAN.
gpio_enable_module_pin(config.can_rx_map.pin, config.can_rx_map.function);
gpio_enable_module_pin(config.can_tx_map.pin, config.can_tx_map.function);
// activate control pins for CAN transceiver
gpio_configure_pin(config.can_shutdown_pin, GPIO_DIR_OUTPUT | GPIO_INIT_LOW); // CAN0 shutdown line
gpio_configure_pin(config.can_standby_pin, GPIO_DIR_OUTPUT | GPIO_INIT_LOW); // CAN0 standby line
// Initialize channel 0
can_bus_init_hardware(channel, ((uint32_t)&mob_ram_ch[channel][0]), CANIF_CHANNEL_MODE_NORMAL, NULL);
CAN_stream_rx[channel]=NULL;
CAN_stream_tx[channel]=NULL;
}
// Start oscillator and enable PLL0, sourced by OSC0
static void local_start_highfreq_clock(void)
{
const scif_pll_opt_t opt = {
.osc = SCIF_OSC0, // Sel Osc0/PLL0 or Osc1/PLL1
.lockcount = 16, // lockcount in main clock for the PLL wait lock
.div = 1, // DIV=1 in the formula
.mul = 6, // MUL=7 in the formula
.pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
.pll_wbwdisable = 0, // pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
.pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
};
// Switch main clock to Osc0.
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
/* Setup PLL0 on Osc0, mul=7 ,no divisor, lockcount=16, ie. (16Mhzx7)/(div2) = 56MHz output */
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
}
// Start PWM generic clock input
static void pwm_start_gc(void)
{
scif_gc_setup(AVR32_SCIF_GCLK_PWM,
SCIF_GCCTRL_PLL0,
AVR32_SCIF_GC_NO_DIV_CLOCK,
0);
// Now enable the generic clock
scif_gc_enable(AVR32_SCIF_GCLK_PWM);
}
/**
* \brief Enable the USB generic clock
*
* \pre The USB generic clock must be configured to 48MHz.
*/
void sysclk_auto_enable_usb(void)
{
// Setup USB GCLK
scif_gc_setup(AVR32_SCIF_GCLK_USBC,
SCIF_GCCTRL_PLL0, AVR32_SCIF_GC_NO_DIV_CLOCK, 0);
// Enable USB GCLK
scif_gc_enable(AVR32_SCIF_GCLK_USBC);
}
/* \brief Set-up a generic clock to run from a high-frequency clock and output it to a gpio pin.
*
*/
static void local_start_gc(void)
{
#if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
// Note: for UC3L devices, the generic clock configurations are handled by the
// SCIF module.
// Setup gc to use the DFLL0 as source clock, divisor enabled, apply a division factor.
// Since the DFLL0 frequency is 96MHz, set the division factor to 2 to have a
// gclk frequency of 48MHz.
scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK, 2);
/* Now enable the generic clock */
scif_gc_enable(EXAMPLE_GCLK_ID);
#elif BOARD == UC3C_EK || BOARD == STK600_RCUC3D
// Note: for UC3 C, D and L series, the generic clock configurations are handled by the
// SCIF module.
/* setup gc on Osc0, no divisor */
scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_PLL0, AVR32_SCIF_GC_NO_DIV_CLOCK, 0);
/* Now enable the generic clock */
scif_gc_enable(EXAMPLE_GCLK_ID);
#else
volatile avr32_pm_t* pm = &AVR32_PM;
/* Setup generic clock on PLL0, with Osc0/PLL0, no divisor */
/*
void pm_gc_setup(volatile avr32_pm_t* pm,
unsigned int gc,
unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
unsigned int diven,
unsigned int div) {
*/
pm_gc_setup(pm,
EXAMPLE_GCLK_ID,
1, // Use Osc (=0) or PLL (=1), here PLL
0, // Sel Osc0/PLL0 or Osc1/PLL1
0, // disable divisor
0); // no divisor
/* Enable Generic clock */
pm_gc_enable(pm, EXAMPLE_GCLK_ID);
#endif
/* Set the GCLOCK function to the GPIO pin */
gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
}
void millis_init(void)
{
//AST generic clock 8MHz / (2*(249+1) = 16kHz
scif_gc_setup(AVR32_SCIF_GCLK_AST,SCIF_GCCTRL_RC8M,AVR32_SCIF_GC_DIV_CLOCK,249);
// Now enable the generic clock
scif_gc_enable(AVR32_SCIF_GCLK_AST);
//set up timer
ast_init_counter(&AVR32_AST,AST_OSC_GCLK,4,counta); //16kHz / (2^(4+1)) = 1kHz
ast_enable(&AVR32_AST);
}
long int pcl_configure_usb_clock(void)
{
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
pm_configure_usb_clock();
return PASS;
#else
#ifdef AVR32_PM_410_H_INCLUDED
const scif_pll_opt_t opt = {
.osc = SCIF_OSC0, // Sel Osc0 or Osc1
.lockcount = 16, // lockcount in main clock for the PLL wait lock
.div = 1, // DIV=1 in the formula
.mul = 5, // MUL=7 in the formula
.pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
.pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
};
/* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */
scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL1 */
scif_pll_enable(SCIF_PLL1);
/* Wait for PLL1 locked */
scif_wait_for_pll_locked(SCIF_PLL1) ;
// Implementation for UC3C parts.
// Setup the generic clock for USB
scif_gc_setup(AVR32_SCIF_GCLK_USB,
SCIF_GCCTRL_PLL1,
AVR32_SCIF_GC_NO_DIV_CLOCK,
0);
// Now enable the generic clock
scif_gc_enable(AVR32_SCIF_GCLK_USB);
return PASS;
#else
return PCL_NOT_SUPPORTED;
#endif
#endif
}
#if UC3L
#else
void pcl_write_gplp(unsigned long gplp, unsigned long value)
{
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
pm_write_gplp(&AVR32_PM,gplp,value);
#else
scif_write_gplp(gplp,value);
#endif
}
static void local_start_gc()
{
// Setup gc on DFLL; the target frequency is 12MHz => divide the DFLL frequency
// by 2 (== EXAMPLE_FDFLL_HZ / EXAMPLE_GCLK_FREQ_HZ).
scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK,
TARGET_DFLL_FREQ_HZ/EXAMPLE_GCLK_FREQ_HZ);
// Now enable the generic clock
scif_gc_enable(EXAMPLE_GCLK_ID);
/* Assign a GPIO to generic clock output */
gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
// Note that gclk1 is GPIO pin 6 pa06 on AT32UC3L064 pin 10 on QFP48.
}
/* \brief Set-up a generic clock to run from RC120M and output it to a gpio pin.
*
*/
static void local_start_gc(void)
{
// Note: for UC3L devices, the generic clock configurations are handled by the
// SCIF module.
// Setup gc to use RC120M as source clock, divisor enabled, apply a division factor.
// Since the RC120M frequency is 120MHz, set the division factor to 4 to have a
// gclk frequency of 30MHz.
scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_RC120M, AVR32_SCIF_GC_DIV_CLOCK, 4);
// Now enable the generic clock
scif_gc_enable(EXAMPLE_GCLK_ID);
// Set the GCLOCK function to the GPIO pin
gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
}
void can_task_init(void)
{
// Setup the generic clock for CAN
scif_gc_setup(AVR32_SCIF_GCLK_CANIF,
SCIF_GCCTRL_OSC0,
AVR32_SCIF_GC_NO_DIV_CLOCK,
0);
// Now enable the generic clock
scif_gc_enable(AVR32_SCIF_GCLK_CANIF);
static const gpio_map_t CAN_GPIO_MAP = {
{AVR32_CANIF_RXLINE_0_0_PIN, AVR32_CANIF_RXLINE_0_0_FUNCTION},
{AVR32_CANIF_TXLINE_0_0_PIN, AVR32_CANIF_TXLINE_0_0_FUNCTION},
{AVR32_CANIF_RXLINE_1_2_PIN, AVR32_CANIF_RXLINE_1_2_FUNCTION},
{AVR32_CANIF_TXLINE_1_2_PIN, AVR32_CANIF_TXLINE_1_2_FUNCTION}
};
// Assign GPIO to CAN.
gpio_enable_module(CAN_GPIO_MAP,
sizeof(CAN_GPIO_MAP) / sizeof(CAN_GPIO_MAP[0]));
can_example_prepare_data_to_receive();
can_example_prepare_data_to_send();
}
static unsigned long init_clock( unsigned long cpuclk_hz )
{
unsigned long ret_val = 0u;
// Program the DFLL and switch the main clock source to the DFLL.
pcl_configure_clocks(&pcl_dfll_freq_param);
#if DEF_TOUCH_QMATRIX == 1
/* Set up the GCLK_CAT for proper QMatrix operation. The GCLK_CAT is not
required to be setup for Autonomous Touch and QTouch Group A/B operation.
Note: for UC3L devices, the generic clock configurations are handled by the
SCIF module. Setup gc to use the DFLL0 as source clock, divisor enabled, apply
a division factor. */
ret_val |= scif_gc_setup(AVR32_SCIF_GCLK_CAT, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK, QM_GCLK_CAT_DIV);
/* Now enable the generic clock */
ret_val |= scif_gc_enable(AVR32_SCIF_GCLK_CAT);
#endif
return (ret_val);
}
/** Main function to configure the CAN, and begin transfers. */
int main(void)
{
/* Initialize the system clocks */
sysclk_init();
/* Setup the generic clock for CAN */
scif_gc_setup(AVR32_SCIF_GCLK_CANIF,
SCIF_GCCTRL_OSC0,
AVR32_SCIF_GC_NO_DIV_CLOCK,
0);
/* Now enable the generic clock */
scif_gc_enable(AVR32_SCIF_GCLK_CANIF);
init_dbg_rs232(FPBA_HZ);
/* Disable all interrupts. */
Disable_global_interrupt();
/* Initialize interrupt vectors. */
INTC_init_interrupts();
static const gpio_map_t CAN_GPIO_MAP = {
{AVR32_CANIF_RXLINE_0_0_PIN, AVR32_CANIF_RXLINE_0_0_FUNCTION},
{AVR32_CANIF_TXLINE_0_0_PIN, AVR32_CANIF_TXLINE_0_0_FUNCTION}
};
/* Assign GPIO to CAN. */
gpio_enable_module(CAN_GPIO_MAP,
sizeof(CAN_GPIO_MAP) / sizeof(CAN_GPIO_MAP[0]));
/* Initialize channel 0 */
can_init(CAN_CHANNEL_EXAMPLE, ((uint32_t)&mob_ram_ch0[0]),
CANIF_CHANNEL_MODE_LISTENING, can_out_callback_channel0);
/* Enable all interrupts. */
Enable_global_interrupt();
print_dbg("\r\nUC3C CAN Examples 1\r\n");
print_dbg(CAN_Wakeup);
/* Initialize CAN Channel 0 */
can_init(CAN_CHANNEL_EXAMPLE, ((uint32_t)&mob_ram_ch0[0]),
CANIF_CHANNEL_MODE_NORMAL, can_out_callback_channel0);
/* Allocate one mob for RX */
appli_rx_msg.handle = can_mob_alloc(CAN_CHANNEL_EXAMPLE);
/* Initialize RX message */
can_rx(CAN_CHANNEL_EXAMPLE, appli_rx_msg.handle, appli_rx_msg.req_type,
appli_rx_msg.can_msg);
/* Enable Async Wake Up Mode */
pm_asyn_wake_up_enable(CAN_WAKEUP_MASK_EXAMPLE);
/* ---------SLEEP MODE PROCEDURE------------- */
/* Disable CAN Channel 0 */
CANIF_disable(CAN_CHANNEL_EXAMPLE);
/* Wait CAN Channel 0 is disabled */
while(!CANIF_channel_enable_status(CAN_CHANNEL_EXAMPLE));
/* Enable Wake-Up Mode */
CANIF_enable_wakeup(CAN_CHANNEL_EXAMPLE);
/* Go to sleep mode. */
SLEEP(AVR32_PM_SMODE_STATIC);
/* ---------SLEEP MODE PROCEDURE------------- */
print_dbg(CAN_WakeupD);
/* Initialize again CAN Channel 0 */
can_init(CAN_CHANNEL_EXAMPLE, ((uint32_t)&mob_ram_ch0[0]),
CANIF_CHANNEL_MODE_NORMAL, can_out_callback_channel0);
/* Allocate one mob for RX */
appli_rx_msg.handle = can_mob_alloc(CAN_CHANNEL_EXAMPLE);
/* Initialize RX message */
can_rx(CAN_CHANNEL_EXAMPLE, appli_rx_msg.handle, appli_rx_msg.req_type,
appli_rx_msg.can_msg);
for (;;) {
/* Do nothing; interrupts handle the DAC conversions */
}
}
/**
* \brief Initializes the ACIFB module with trigger
* - Start the GCLK for ACIFB
* - Initialize the trigger mode & compare interrupts for ACIFB
*
* \retval STATUS_OK Configuration OK
* \retval ERR_TIMEOUT Timeout on configuring ACIFB module
* \retval ERR_BUSY ACIFB module unable to configure the trigger
*/
static status_code_t ac_init()
{
/* struct genclk_config gcfg; */
uint32_t div = sysclk_get_pba_hz() / AC_GCLK_FREQUENCY;
scif_gc_setup(AC_GCLK_ID, AC_GCLK_SRC, AVR32_GC_DIV_CLOCK, div);
/* Now enable the generic clock */
scif_gc_enable(AC_GCLK_ID);
/* GPIO pin/acifb - function map. */
static const gpio_map_t ACIFB_GPIO_MAP = {
{EXAMPLE_ACIFBP_PIN, EXAMPLE_ACIFBP_FUNCTION},
{EXAMPLE_ACIFBN_PIN, EXAMPLE_ACIFBN_FUNCTION},
};
/* ACIFB Configuration */
const acifb_t acifb_opt = {
.sut = 6, /* Resolution mode */
.actest = TESTMODE_OFF,
.eventen = true
};
/* ACIFB Channel Configuration */
const acifb_channel_t acifb_channel_opt = {
/* Filter length */
.filter_len = 0,
/* Hysteresis value */
.hysteresis_value = 0,
/* Output event when ACOUT is zero? */
.event_negative = false,
/* Output event when ACOUT is one? */
.event_positive = false,
/* Set the positive input */
.positive_input = PI_ACP,
/* Set the negative input */
.negative_input = NI_ACN,
/* Set the comparator mode */
.mode = MODE_EVENT_TRIGGERED,
/* Interrupt settings */
.interrupt_settings = IS_VINP_LT_VINN,
/* Analog comparator channel number */
.ac_n = EXAMPLE_ACIFB_CHANNEL
};
/* Enable Analog Comparator clock */
sysclk_enable_pba_module(SYSCLK_ACIFB);
/* Disable pullup on ACIFB channel input pins */
gpio_disable_pin_pull_up(EXAMPLE_ACIFBP_PIN);
gpio_disable_pin_pull_up(EXAMPLE_ACIFBN_PIN);
/* Enable the ACIFB pins */
gpio_enable_module(ACIFB_GPIO_MAP,
sizeof(ACIFB_GPIO_MAP) / sizeof(ACIFB_GPIO_MAP[0]));
/* Configure the ACIFB peripheral */
acifb_setup_and_enable(acifb, &acifb_opt);
/* Configure the ACIFB channel with interrupt & trigger */
acifb_channels_setup(acifb, &acifb_channel_opt, AC_NB_CHANNELS);
/* Disable global interrupts */
cpu_irq_disable();
/*
* Initialize the interrupt vectors
* Note: This function adds nothing for IAR as the interrupts are
* handled by the IAR compiler itself. It provides an abstraction
* between GCC & IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_initialize_vectors();
/*
* Register the ACIFB interrupt handler
* Note: This function adds nothing for IAR as the interrupts are
* handled by the IAR compiler itself. It provides an abstraction
* between GCC & IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_register_handler(&ACIFB_interrupt_handler, AVR32_ACIFB_IRQ,
AC_INTERRUPT_PRIORITY);
/* Enable Analog Comparator Channel interrupt */
acifb_enable_comparison_interrupt(acifb, EXAMPLE_ACIFB_CHANNEL);
/* Enable global interrupts */
cpu_irq_enable();
return STATUS_OK;
} /* End of ac_init() */
/**
* \brief Asynchronous Timer Initialization
* - Start the 32KHz Oscillator
* - Initializes the AST module with periodic trigger events
*
* \retval STATUS_OK Configuration OK
* \retval ERR_BUSY Error in configuring the AST module
*/
static status_code_t ast_init()
{
/* Initial Count value to write in AST */
unsigned long ast_counter = 0;
/* Set the prescaler to set a periodic trigger from AST */
avr32_ast_pir0_t pir = {
.insel = AST_TRIGGER_PRESCALER
};
/* Set the OSC32 parameters */
scif_osc32_opt_t osc32_opt = {
.mode = SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR,
.startup = OSC32_STARTUP_8192,
.pinsel = BOARD_OSC32_PINSEL,
.en1k = false,
.en32k = true
};
/* Enable the 32KHz Oscillator */
scif_start_osc32(&osc32_opt, true);
/* Enable the Peripheral Event System Clock */
sysclk_enable_hsb_module(SYSCLK_EVENT);
/* Enable PBA clock for AST clock to switch its source */
sysclk_enable_pba_module(SYSCLK_AST);
/* Initialize the AST in counter mode */
if (!ast_init_counter(&AVR32_AST, AST_CLOCK_SOURCE, AST_PRESCALER,
ast_counter)) {
return ERR_BUSY;
}
/* Initialize the periodic value register with the prescaler */
ast_set_periodic0_value(&AVR32_AST, pir);
/* Enable the AST periodic event */
ast_enable_periodic0(&AVR32_AST);
/* Clear All AST Interrupt request and clear SR */
ast_clear_all_status_flags(&AVR32_AST);
/* Enable the AST */
ast_enable(&AVR32_AST);
/* Disable PBA clock for AST after switching its source to OSC32 */
sysclk_disable_pba_module(SYSCLK_AST);
return STATUS_OK;
} /* End of ast_init() */
/**
* \brief Low Power Configuration
* Initializes the power saving measures to reduce power consumption
* - Enable pull-ups on GPIO pins
* - Disable the clocks to unwanted modules
* - Disable internal voltage regulator when in 1.8V supply mode
*/
static void power_save_measures_init()
{
uint8_t i;
uint32_t gpio_mask[AVR32_GPIO_PORT_LENGTH] = {0};
/*
* Enable internal pull-ups on all unused GPIO pins
* Note: Pull-ups on Oscillator or JTAG pins can be enabled only if they
* are not used as an oscillator or JTAG pin respectively.
*/
for (i = 0; i < (sizeof(gpio_used_pins) / sizeof(uint32_t)); i++) {
gpio_mask[gpio_used_pins[i] >>
5] |= 1 << (gpio_used_pins[i] & 0x1F);
}
for (i = 0; i < AVR32_GPIO_PORT_LENGTH; i++) {
gpio_configure_group(i, ~(gpio_mask[i]),
GPIO_PULL_UP | GPIO_DIR_INPUT);
}
/* Disable OCD clock which is not disabled by sysclk service */
sysclk_disable_cpu_module(SYSCLK_OCD);
#if POWER_SUPPLY_MODE_1_8V
/*
* When using 1.8V Single supply mode, the Voltage Regulator can be
* shut-down using the code below, in-order to save power.
* See Voltage Regulator Calibration Register in datasheet for more
*info.
* CAUTION: When using 3.3V Single supply mode, the Voltage Regulator
* cannot be shut-down and the application will hang in this loop.
*/
uint32_t tmp = (AVR32_SCIF.vregcr);
tmp &= (~(1 << 5 | 1 << 18));
AVR32_SCIF.unlock = 0xAA000000 | AVR32_SCIF_VREGCR;
AVR32_SCIF.vregcr = tmp;
/* Wait until internal voltage regulator is disabled. */
while ((AVR32_SCIF.vregcr & 0x00040020)) {
}
#endif
} /* End of power_save_measures_init() */
void ecu_can_init(void) {
/* Setup the generic clock for CAN output */
scif_gc_setup(
AVR32_SCIF_GCLK_CANIF,
SCIF_GCCTRL_OSC0,
AVR32_SCIF_GC_NO_DIV_CLOCK,
0
);
/* Now enable the generic clock input for the CAN module */
scif_gc_enable(AVR32_SCIF_GCLK_CANIF);
static const gpio_map_t CAN_GPIO_MAP = {
{CAN0_RX_PIN, CAN0_RX_FUNCTION},
{CAN0_TX_PIN, CAN0_TX_FUNCTION},
{CAN1_RX_PIN, CAN1_RX_FUNCTION},
{CAN1_TX_PIN, CAN1_TX_FUNCTION}
};
/* Assign GPIO to CAN. */
gpio_enable_module(CAN_GPIO_MAP, sizeof(CAN_GPIO_MAP) / sizeof(CAN_GPIO_MAP[0]));
/* Initialize interrupt vectors. */
INTC_init_interrupts();
/* Allocate channel message box */
mob_rx_speed_sens_fl.handle = 0;
mob_rx_speed_sens_fr.handle = 1;
mob_rx_speed_sens_rl.handle = 2;
mob_rx_speed_sens_rr.handle = 3;
mob_rx_dash_pri.handle = 4;
mob_tx_dash.handle = 5;
mob_rx_trq_sens0.handle = 6;
mob_rx_trq_sens1.handle = 7;
mob_ecu_slow_data.handle = 8;
mob_rx_bms_precharge.handle = 9;
mob_brk.handle = 10;
mob_ecu_fast_data.handle = 11;
mob_rx_bms_battvolt.handle = 12;
mob_rx_bspd.handle = 13;
mob_rx_dash_data.handle = 14;
mob_slip_current.handle = 15;
/* Initialize CAN channels */
can_init(CAN_BUS_0, ((uint32_t)&mob_ram_ch0[0]), CANIF_CHANNEL_MODE_NORMAL, can_out_callback_channel0);
can_init(CAN_BUS_1, ((uint32_t)&mob_ram_ch1[0]), CANIF_CHANNEL_MODE_NORMAL, can_out_callback_channel1);
/* Prepare for message reception */
can_rx(
CAN_BUS_1
, mob_rx_speed_sens_fl.handle
, mob_rx_speed_sens_fl.req_type
, mob_rx_speed_sens_fl.can_msg
);
can_rx(
CAN_BUS_1
, mob_rx_speed_sens_fr.handle
, mob_rx_speed_sens_fr.req_type
, mob_rx_speed_sens_fr.can_msg
);
can_rx(
CAN_BUS_1
, mob_rx_speed_sens_rl.handle
, mob_rx_speed_sens_rl.req_type
, mob_rx_speed_sens_rl.can_msg
);
can_rx(
CAN_BUS_1
, mob_rx_speed_sens_rr.handle
, mob_rx_speed_sens_rr.req_type
, mob_rx_speed_sens_rr.can_msg
);
can_rx(
CAN_BUS_0
, mob_rx_dash_pri.handle
, mob_rx_dash_pri.req_type
, mob_rx_dash_pri.can_msg
);
can_rx(
CAN_BUS_0
, mob_rx_dash_data.handle
, mob_rx_dash_data.req_type
, mob_rx_dash_data.can_msg
);
can_rx(
CAN_BUS_0
, mob_rx_trq_sens0.handle
, mob_rx_trq_sens0.req_type
, mob_rx_trq_sens0.can_msg
);
can_rx(
CAN_BUS_1
, mob_rx_trq_sens1.handle
, mob_rx_trq_sens1.req_type
, mob_rx_trq_sens1.can_msg
);
can_rx(
CAN_BUS_1
, mob_rx_bms_precharge.handle
, mob_rx_bms_precharge.req_type
, mob_rx_bms_precharge.can_msg
);
can_rx(
CAN_BUS_1
, mob_rx_bms_battvolt.handle
, mob_rx_bms_battvolt.req_type
, mob_rx_bms_battvolt.can_msg
);
can_rx(
CAN_BUS_1
, mob_brk.handle
, mob_brk.req_type
, mob_brk.can_msg
);
can_rx(
CAN_BUS_0
, mob_rx_bspd.handle
, mob_rx_bspd.req_type
, mob_rx_bspd.can_msg
);
asm("nop");
}
/*! \brief Main function. Execution starts here.
*/
int main(void)
{
// Options for QDEC timer Mode
static const qdec_timer_opt_t QUADRATURE_TIMER_OPT =
{
.upd = false, // Up/Down Mode Timer Disabled.
.tsdir = QDEC_TSIR_DOWN, // Count Down Timer.
.filten = false, // Disable filtering.
.evtrge = false, // Disable event triggering.
.rcce = true, // Enable Position Compare.
.pcce = true, // Enable Revolution Compare.
};
// Options for QDEC Interrupt Management
static const qdec_interrupt_t QDEC_INTERRUPT =
{
.cmp = 1, // Enable Compare Interrupt.
.cap = 0, // Disable Capture Interrupt.
.pcro = 0, // Disable Position Roll-over Interrupt.
.rcro = 0 // Disable Counter Roll-over Interrupt.
};
// Configure system clocks.
if (pcl_configure_clocks(&pcl_freq_param) != PASS) {
while(1);
}
// Setup the generic clock for QDEC
scif_gc_setup(AVR32_SCIF_GCLK_QDEC0,
SCIF_GCCTRL_OSC0,
AVR32_SCIF_GC_NO_DIV_CLOCK,
0);
// Now enable the generic clock
scif_gc_enable(AVR32_SCIF_GCLK_QDEC0);
Disable_global_interrupt();
// Initialize interrupt vectors.
INTC_init_interrupts();
// Register the QDEC interrupt handler to the interrupt controller.
INTC_register_interrupt(&qdec_int_handler, AVR32_QDEC0_IRQ, AVR32_INTC_INT0);
Enable_global_interrupt();
// Initialization of counter value as a 32-bit counter to 0x0000FFFF (Rc=0x0000/Pc=0xFFFF)
qdec_write_rc_cnt(qdec,0x0000);
qdec_write_pc_cnt(qdec,0xffff);
// Initialization of compare value to 0x0 as the interrupt will be generated when the counter value will be equal to 0
qdec_write_rc_cmp(qdec,0);
qdec_write_pc_cmp(qdec,0);
// Initialize the QDEC in quadrature decoder mode.
qdec_init_timer_mode(qdec,&QUADRATURE_TIMER_OPT);
// Configure the QDEC interrupts.
qdec_configure_interrupts(qdec,&QDEC_INTERRUPT);
// Start the QDEC.
qdec_software_trigger(qdec);
unsigned int pc_cmp = 0;
while(1)
{
// Compare Interrupt Flag
if(flag_qdec == 1)
{
gpio_tgl_gpio_pin(LED0_GPIO); // Check signal on oscilloscope.
if (pc_cmp < 0xffff ) pc_cmp += 0x100; // Increase PC CMP
else pc_cmp = 0; // Start the signal pattern over.
qdec_write_pc_cmp(qdec,pc_cmp); // Reload Compare Flag
flag_qdec = 0; // Reset Interrupt Flag
}
}
}
