int qti_pfk_ice_set_key(uint32_t index, uint8_t *key, uint8_t *salt)
{
struct scm_desc desc = {0};
int ret;
char *tzbuf_key = (char *)ice_key;
char *tzbuf_salt = (char *)ice_salt;
uint32_t smc_id = 0;
u32 tzbuflen_key = sizeof(ice_key);
u32 tzbuflen_salt = sizeof(ice_salt);
if (index < MIN_ICE_KEY_INDEX || index > MAX_ICE_KEY_INDEX)
return -EINVAL;
if (!key || !salt)
return -EINVAL;
if (!tzbuf_key || !tzbuf_salt)
return -ENOMEM;
memset(tzbuf_key, 0, tzbuflen_key);
memset(tzbuf_salt, 0, tzbuflen_salt);
memcpy(ice_key, key, tzbuflen_key);
memcpy(ice_salt, salt, tzbuflen_salt);
dmac_flush_range(tzbuf_key, tzbuf_key + tzbuflen_key);
dmac_flush_range(tzbuf_salt, tzbuf_salt + tzbuflen_salt);
smc_id = TZ_ES_SET_ICE_KEY_ID;
pr_debug(" %s , smc_id = 0x%x\n", __func__, smc_id);
desc.arginfo = TZ_ES_SET_ICE_KEY_PARAM_ID;
desc.args[0] = index;
desc.args[1] = virt_to_phys(tzbuf_key);
desc.args[2] = tzbuflen_key;
desc.args[3] = virt_to_phys(tzbuf_salt);
desc.args[4] = tzbuflen_salt;
ret = scm_call2_atomic(smc_id, &desc);
pr_debug(" %s , ret = %d\n", __func__, ret);
if (ret) {
pr_err("%s: Error: 0x%x\n", __func__, ret);
smc_id = TZ_ES_INVALIDATE_ICE_KEY_ID;
desc.arginfo = TZ_ES_INVALIDATE_ICE_KEY_PARAM_ID;
desc.args[0] = index;
scm_call2_atomic(smc_id, &desc);
}
return ret;
}
int qti_pfk_ice_invalidate_key(uint32_t index)
{
struct scm_desc desc = {0};
int ret;
uint32_t smc_id = 0;
if (index < MIN_ICE_KEY_INDEX || index > MAX_ICE_KEY_INDEX)
return -EINVAL;
smc_id = TZ_ES_INVALIDATE_ICE_KEY_ID;
pr_debug(" %s , smc_id = 0x%x\n", __func__, smc_id);
desc.arginfo = TZ_ES_INVALIDATE_ICE_KEY_PARAM_ID;
desc.args[0] = index;
ret = qcom_ice_setup_ice_hw("ufs", true);
if (ret)
pr_err("%s: could not enable clocks: 0x%x\n", __func__, ret);
ret = scm_call2_atomic(smc_id, &desc);
qcom_ice_setup_ice_hw("ufs", false);
pr_debug(" %s , ret = %d\n", __func__, ret);
if (ret)
pr_err("%s: Error: 0x%x\n", __func__, ret);
return ret;
}
static int gen_sec_wdt_scm(const char *val, struct kernel_param *kp)
{
struct scm_desc desc;
desc.args[0] = 0;
desc.arginfo = SCM_ARGS(1);
pr_info("%s\n", __func__);
scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_BOOT,
SCM_SVC_SEC_WDOG_TRIG), &desc);
pr_err("%s failed\n", __func__);
return -EIO;
}
static int simulate_secure_wdog_bite(void)
{ int ret;
struct scm_desc desc = {
.args[0] = 0,
.arginfo = SCM_ARGS(1),
};
pr_emerg("simulating secure watch dog bite using scm_call\n");
if (!is_scm_armv8())
ret = scm_call_atomic2(SCM_SVC_BOOT,
SCM_SVC_SEC_WDOG_TRIG, 0, 0);
else
ret = scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_BOOT,
SCM_SVC_SEC_WDOG_TRIG), &desc);
/* if we hit, scm_call has failed */
pr_emerg("simulation of secure watch dog bite failed\n");
return ret;
}
#else
int simulate_secure_wdog_bite(void)
{
return 0;
}
#endif
#if defined(CONFIG_ARCH_MSM8226) || defined(CONFIG_ARCH_MSM8974)
/*
* Misc data structures needed for simulating bus timeout in
* camera
*/
#define HANG_ADDRESS 0xfda10000
struct clk_pair {
const char *dev;
const char *clk;
};
static struct clk_pair bus_timeout_camera_clocks_on[] = {
/*
* gcc_mmss_noc_cfg_ahb_clk should be on but right
* now this clock is on by default and not accessable.
* Update this table if gcc_mmss_noc_cfg_ahb_clk is
* ever not enabled by default!
*/
{
.dev = "fda0c000.qcom,cci",
.clk = "camss_top_ahb_clk",
},
{
.dev = "fda10000.qcom,vfe",
void sec_do_bypass_sdi_execution_in_low(void)
{
int ret;
struct scm_desc desc = {
.args[0] = 1,
.args[1] = 0,
.arginfo = SCM_ARGS(2),
};
/* Needed to bypass debug image on some chips */
if (!is_scm_armv8())
ret = scm_call_atomic2(SCM_SVC_BOOT,
SCM_WDOG_DEBUG_BOOT_PART, 1, 0);
else
ret = scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_BOOT,
SCM_WDOG_DEBUG_BOOT_PART), &desc);
if (ret)
pr_err("Failed to disable wdog debug: %d\n", ret);
}
int __init sec_debug_init(void)
{
int ret;
ret=sec_dt_addr_init();
if (ret<0)
return ret;
register_reboot_notifier(&nb_reboot_block);
atomic_notifier_chain_register(&panic_notifier_list, &nb_panic_block);
if (!enable) {
sec_do_bypass_sdi_execution_in_low();
return -EPERM;
}
#ifdef CONFIG_SEC_DEBUG_SCHED_LOG
__init_sec_debug_log();
#endif
sec_debug_set_upload_magic(SECDEBUG_MODE);
sec_debug_set_upload_cause(UPLOAD_CAUSE_INIT);
return 0;
}