void enable_sead_irq(unsigned int irq_nr)
{
if (irq_nr == SEADINT_UART0)
set_cp0_status(0x00000400);
else
if (irq_nr == SEADINT_UART1)
set_cp0_status(0x00000800);
}
asmlinkage void __init
init_arch(int argc, char **argv, char **envp, int *prom_vec)
{
unsigned int s;
/* Determine which MIPS variant we are running on. */
cpu_probe();
prom_init(argc, argv, envp, prom_vec);
#ifdef CONFIG_SGI_IP22
sgi_sysinit();
#endif
cpu_report();
/*
* Determine the mmu/cache attached to this machine,
* then flush the tlb and caches. On the r4xx0
* variants this also sets CP0_WIRED to zero.
*/
loadmmu();
/* Disable coprocessors and set FPU for 16/32 FPR register model */
clear_cp0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
set_cp0_status(ST0_CU0);
start_kernel();
}
asmlinkage void __init init_arch(int argc, char **argv, char **envp,
int *prom_vec)
{
/* Determine which MIPS variant we are running on. */
cpu_probe();
prom_init(argc, argv, envp, prom_vec);
#ifdef CONFIG_SGI_IP22
sgi_sysinit();
#endif
cpu_report();
/*
* Determine the mmu/cache attached to this machine, then flush the
* tlb and caches. On the r4xx0 variants this also sets CP0_WIRED to
* zero.
*/
load_mmu();
/*
* On IP27, I am seeing the TS bit set when the kernel is loaded.
* Maybe because the kernel is in ckseg0 and not xkphys? Clear it
* anyway ...
*/
clear_cp0_status(ST0_BEV|ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3);
set_cp0_status(ST0_CU0|ST0_KX|ST0_SX|ST0_FR);
start_kernel();
}
void nec_korva_restart(char *command)
{
set_cp0_status(ST0_BEV | ST0_ERL);
change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
}
void flush_thread(void)
{
/* Forget lazy fpu state */
if (last_task_used_math == current) {
set_cp0_status(ST0_CU1, ST0_CU1);
__asm__ __volatile__("cfc1\t$0,$31");
last_task_used_math = NULL;
}
}
static void enable_irq4(unsigned int irq)
{
set_cp0_status(STATUSF_IP4);
if (irq == 2) {
outl(inl(TX3912_INT2_CLEAR) | TX3912_INT2_UARTA_TX_BITS,
TX3912_INT2_CLEAR);
outl(inl(TX3912_INT2_ENABLE) | TX3912_INT2_UARTA_TX_BITS,
TX3912_INT2_ENABLE);
}
}
void
ddb5477_irq_setup(void)
{
db_run(printk("ddb5477_irq_setup invoked.\n"));
/* by default, we disable all interrupts and route all vrc5477
* interrupts to pin 0 (irq 2) */
ddb_out32(DDB_INTCTRL0, 0);
ddb_out32(DDB_INTCTRL1, 0);
ddb_out32(DDB_INTCTRL2, 0);
ddb_out32(DDB_INTCTRL3, 0);
clear_cp0_status(0xff00);
set_cp0_status(0x0400);
/* setup PCI interrupt attributes */
set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
/*
* for debugging purpose, we enable several error interrupts
* and route them to pin 1. (IP3)
*/
/* cpu parity check - 0 */
ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
/* cpu no-target decode - 1 */
ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
/* local bus read time-out - 7 */
ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
/* PCI SERR# - 14 */
ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
/* PCI internal error - 15 */
ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
/* IOPCI SERR# - 30 */
ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
/* IOPCI internal error - 31 */
ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
/* init all controllers */
mips_cpu_irq_init(0);
vrc5477_irq_init(8);
/* hook up the first-level interrupt handler */
set_except_vector(0, ddb5477_handle_int);
}
void __init mips_timer_setup(struct irqaction *irq)
{
/* we are using the cpu counter for timer interrupts */
irq->handler = no_action; /* we use our own handler */
setup_irq(MIPS_CPU_TIMER_IRQ, irq);
/* to generate the first timer interrupt */
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
set_cp0_status(ALLINTS);
}
void au1000_restart(char *command)
{
/* Set all integrated peripherals to disabled states */
u32 prid = read_32bit_cp0_register(CP0_PRID);
printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
switch (prid & 0xFF000000)
{
case 0x00000000: /* Au1000 */
outl(0x02, 0xb0000010); /* ac97_enable */
outl(0x08, 0xb017fffc); /* usbh_enable - early errata */
asm("sync");
outl(0x00, 0xb017fffc); /* usbh_enable */
outl(0x00, 0xb0200058); /* usbd_enable */
outl(0x00, 0xb0300040); /* ir_enable */
outl(0x00, 0xb0520000); /* macen0 */
outl(0x00, 0xb0520004); /* macen1 */
outl(0x00, 0xb1000008); /* i2s_enable */
outl(0x00, 0xb1100100); /* uart0_enable */
outl(0x00, 0xb1200100); /* uart1_enable */
outl(0x00, 0xb1300100); /* uart2_enable */
outl(0x00, 0xb1400100); /* uart3_enable */
outl(0x02, 0xb1600100); /* ssi0_enable */
outl(0x02, 0xb1680100); /* ssi1_enable */
outl(0x00, 0xb1900020); /* sys_freqctrl0 */
outl(0x00, 0xb1900024); /* sys_freqctrl1 */
outl(0x00, 0xb1900028); /* sys_clksrc */
outl(0x00, 0xb1900100); /* sys_pininputen */
break;
case 0x01000000: /* Au1500 */
outl(0x02, 0xb0000010); /* ac97_enable */
outl(0x08, 0xb017fffc); /* usbh_enable - early errata */
asm("sync");
outl(0x00, 0xb017fffc); /* usbh_enable */
outl(0x00, 0xb0200058); /* usbd_enable */
outl(0x00, 0xb1520000); /* macen0 */
outl(0x00, 0xb1520004); /* macen1 */
outl(0x00, 0xb1100100); /* uart0_enable */
outl(0x00, 0xb1400100); /* uart3_enable */
outl(0x00, 0xb1900020); /* sys_freqctrl0 */
outl(0x00, 0xb1900024); /* sys_freqctrl1 */
outl(0x00, 0xb1900028); /* sys_clksrc */
outl(0x00, 0xb1900100); /* sys_pininputen */
default:
break;
}
set_cp0_status((ST0_BEV | ST0_ERL));
set_cp0_config(CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
}
void prom_init_secondary(void)
{
/* Set up kseg0 to be cachable coherent */
clear_cp0_config(CONF_CM_CMASK);
set_cp0_config(0x5);
/* Enable interrupts for lines 0-4 */
clear_cp0_status(0xe000);
set_cp0_status(0x1f01);
}
void __init init_IRQ(void)
{
int i;
unsigned long flags;
memset(irq_desc, 0, sizeof(irq_desc));
set_except_vector(0, it8172_IRQ);
init_generic_irq();
/* mask all interrupts */
it8172_hw0_icregs->lb_mask = 0xffff;
it8172_hw0_icregs->lpc_mask = 0xffff;
it8172_hw0_icregs->pci_mask = 0xffff;
it8172_hw0_icregs->nmi_mask = 0xffff;
/* make all interrupts level triggered */
it8172_hw0_icregs->lb_trigger = 0;
it8172_hw0_icregs->lpc_trigger = 0;
it8172_hw0_icregs->pci_trigger = 0;
it8172_hw0_icregs->nmi_trigger = 0;
/* active level setting */
/* uart, keyboard, and mouse are active high */
it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
it8172_hw0_icregs->lb_level |= 0x20;
/* keyboard and mouse are edge triggered */
it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
#if 0
// Enable this piece of code to make internal USB interrupt
// edge triggered.
it8172_hw0_icregs->pci_trigger |=
(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
it8172_hw0_icregs->pci_level &=
~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
#endif
for (i = 0; i <= IT8172_LAST_IRQ; i++) {
irq_desc[i].handler = &it8172_irq_type;
}
irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type;
set_cp0_status(ALLINTS_NOTIMER);
#ifdef CONFIG_REMOTE_DEBUG
/* If local serial I/O used for debug port, enter kgdb at once */
puts("Waiting for kgdb to connect...");
set_debug_traps();
breakpoint();
#endif
}
void __init init_IRQ(void)
{
/* Invoke board-specific irq setup */
irq_setup();
#ifdef CONFIG_REMOTE_DEBUG
extern void breakpoint(void);
extern void set_debug_traps(void);
extern void rs_kgdb_hook(void);
rs_kgdb_hook();
clear_cp0_status(STATUSF_IP2);
clear_cp0_status(STATUSF_IP3);
clear_cp0_status(STATUSF_IP4);
clear_cp0_status(STATUSF_IP5);
clear_cp0_status(STATUSF_IP6);
clear_cp0_status(STATUSF_IP7);
printk("Wait for gdb client connection ...\n");
set_debug_traps();
set_cp0_status(STATUSF_IP2);
set_cp0_status(STATUSF_IP3);
set_cp0_status(STATUSF_IP4);
set_cp0_status(STATUSF_IP5);
set_cp0_status(STATUSF_IP6);
set_cp0_status(STATUSF_IP7);
breakpoint();
#endif
}
void __init it8172_timer_setup(struct irqaction *irq)
{
puts("timer_setup\n");
put32(NR_IRQS);
puts("");
/* we are using the cpu counter for timer interrupts */
setup_irq(MIPS_CPU_TIMER_IRQ, irq);
/* to generate the first timer interrupt */
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
set_cp0_status(ALLINTS);
}
int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
unsigned long unused,
struct task_struct * p, struct pt_regs * regs)
{
struct pt_regs * childregs;
long childksp;
extern void save_fp(void*);
childksp = (unsigned long)p + KERNEL_STACK_SIZE - 32;
if (last_task_used_math == current) {
set_cp0_status(ST0_CU1, ST0_CU1);
save_fp(p);
}
/* set up new TSS. */
childregs = (struct pt_regs *) childksp - 1;
*childregs = *regs;
childregs->regs[7] = 0; /* Clear error flag */
if(current->personality == PER_LINUX) {
childregs->regs[2] = 0; /* Child gets zero as return value */
regs->regs[2] = p->pid;
} else {
/* Under IRIX things are a little different. */
childregs->regs[2] = 0;
childregs->regs[3] = 1;
regs->regs[2] = p->pid;
regs->regs[3] = 0;
}
if (childregs->cp0_status & ST0_CU0) {
childregs->regs[28] = (unsigned long) p;
childregs->regs[29] = childksp;
p->thread.current_ds = KERNEL_DS;
} else {
childregs->regs[29] = usp;
p->thread.current_ds = USER_DS;
}
p->thread.reg29 = (unsigned long) childregs;
p->thread.reg31 = (unsigned long) ret_from_fork;
/*
* New tasks loose permission to use the fpu. This accelerates context
* switching for most programs since they don't use the fpu.
*/
p->thread.cp0_status = read_32bit_cp0_register(CP0_STATUS) &
~(ST0_CU3|ST0_CU2|ST0_CU1|KU_MASK);
childregs->cp0_status &= ~(ST0_CU3|ST0_CU2|ST0_CU1);
return 0;
}
void __init cpu_time_init(void)
{
lboard_t *board;
klcpu_t *cpu;
int cpuid;
/* Don't use ARCS. ARCS is fragile. Klconfig is simple and sane. */
board = find_lboard(KL_CONFIG_INFO(get_nasid()), KLTYPE_IP27);
if (!board)
panic("Can't find board info for myself.");
cpuid = LOCAL_HUB_L(PI_CPU_NUM) ? IP27_CPU0_INDEX : IP27_CPU1_INDEX;
cpu = (klcpu_t *) KLCF_COMP(board, cpuid);
if (!cpu)
panic("No information about myself?");
printk("CPU %d clock is %dMHz.\n", smp_processor_id(), cpu->cpu_speed);
set_cp0_status(SRB_TIMOCLK);
}
void __init init_IRQ(void)
{
int i;
unsigned long cp0_status;
cp0_status = read_32bit_cp0_register(CP0_STATUS);
memset(irq_desc, 0, sizeof(irq_desc));
set_except_vector(0, au1000_IRQ);
init_generic_irq();
/*
* Setup high priority interrupts on int_request0; low priority on
* int_request1
*/
for (i = 0; i <= NR_IRQS; i++) {
switch (i) {
case AU1000_MAC0_DMA_INT:
case AU1000_MAC1_DMA_INT:
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
default: /* active high, level interrupt */
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 1);
irq_desc[i].handler = &level_irq_type;
break;
}
}
set_cp0_status(ALLINTS);
#ifdef CONFIG_REMOTE_DEBUG
/* If local serial I/O used for debug port, enter kgdb at once */
puts("Waiting for kgdb to connect...");
set_debug_traps();
breakpoint();
#endif
}
static void
mips_cpu_irq_enable(unsigned int irq)
{
clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
set_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
}
void __init init_IRQ(void)
{
int i;
unsigned long cp0_status;
extern char except_vec0_au1000;
cp0_status = read_32bit_cp0_register(CP0_STATUS);
memset(irq_desc, 0, sizeof(irq_desc));
set_except_vector(0, au1000_IRQ);
init_generic_irq();
for (i = 0; i <= AU1000_MAX_INTR; i++) {
switch (i) {
case AU1000_UART0_INT:
case AU1000_UART3_INT:
#ifdef CONFIG_MIPS_PB1000
case AU1000_UART1_INT:
case AU1000_UART2_INT:
case AU1000_SSI0_INT:
case AU1000_SSI1_INT:
#endif
#ifdef CONFIG_MIPS_PB1100
case AU1000_UART1_INT:
case AU1000_SSI0_INT:
case AU1000_SSI1_INT:
#endif
case AU1000_DMA_INT_BASE:
case AU1000_DMA_INT_BASE+1:
case AU1000_DMA_INT_BASE+2:
case AU1000_DMA_INT_BASE+3:
case AU1000_DMA_INT_BASE+4:
case AU1000_DMA_INT_BASE+5:
case AU1000_DMA_INT_BASE+6:
case AU1000_DMA_INT_BASE+7:
case AU1000_IRDA_TX_INT:
case AU1000_IRDA_RX_INT:
case AU1000_MAC0_DMA_INT:
#ifdef CONFIG_MIPS_PB1000
case AU1000_MAC1_DMA_INT:
#endif
#ifdef CONFIG_MIPS_PB1500
case AU1000_MAC1_DMA_INT:
#endif
case AU1500_GPIO_204:
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
#ifdef CONFIG_MIPS_PB1000
case AU1000_GPIO_15:
#endif
case AU1000_USB_HOST_INT:
#ifdef CONFIG_MIPS_PB1500
case AU1000_PCI_INTA:
case AU1000_PCI_INTB:
case AU1000_PCI_INTC:
case AU1000_PCI_INTD:
case AU1500_GPIO_201:
case AU1500_GPIO_202:
case AU1500_GPIO_203:
case AU1500_GPIO_205:
case AU1500_GPIO_207:
#endif
#ifdef CONFIG_MIPS_PB1100
case AU1000_GPIO_9: // PCMCIA Card Fully_Interted#
case AU1000_GPIO_10: // PCMCIA_STSCHG#
case AU1000_GPIO_11: // PCMCIA_IRQ#
case AU1000_GPIO_13: // DC_IRQ#
case AU1000_GPIO_23: // 2-wire SCL
#endif
setup_local_irq(i, INTC_INT_LOW_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
case AU1000_ACSYNC_INT:
case AU1000_AC97C_INT:
case AU1000_TOY_INT:
case AU1000_TOY_MATCH0_INT:
case AU1000_TOY_MATCH1_INT:
case AU1000_USB_DEV_SUS_INT:
case AU1000_USB_DEV_REQ_INT:
case AU1000_RTC_INT:
case AU1000_RTC_MATCH0_INT:
case AU1000_RTC_MATCH1_INT:
case AU1000_RTC_MATCH2_INT:
setup_local_irq(i, INTC_INT_RISE_EDGE, 0);
irq_desc[i].handler = &rise_edge_irq_type;
break;
// Careful if you change match 2 request!
// The interrupt handler is called directly
// from the low level dispatch code.
case AU1000_TOY_MATCH2_INT:
setup_local_irq(i, INTC_INT_RISE_EDGE, 1);
irq_desc[i].handler = &rise_edge_irq_type;
break;
default: /* active high, level interrupt */
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
}
}
set_cp0_status(ALLINTS);
#ifdef CONFIG_REMOTE_DEBUG
/* If local serial I/O used for debug port, enter kgdb at once */
puts("Waiting for kgdb to connect...");
set_debug_traps();
breakpoint();
#endif
}
static void enable_cpu_irq(unsigned int irq)
{
set_cp0_status(STATUSF_IP7);
}
