/* Set the modem control signals state of uart controller. */
void tegra_uart_set_mctrl(struct uart_port *uport, unsigned int mctrl)
{
unsigned long flags;
struct tegra_uart_port *t;
t = container_of(uport, struct tegra_uart_port, uport);
if (t->uart_state != TEGRA_UART_OPENED) {
dev_err(t->uport.dev, "Uart is in invalid state\n");
return;
}
spin_lock_irqsave(&uport->lock, flags);
if (mctrl & TIOCM_RTS) {
t->rts_active = true;
set_rts(t, true);
} else {
t->rts_active = false;
set_rts(t, false);
}
if (mctrl & TIOCM_DTR)
set_dtr(t, true);
else
set_dtr(t, false);
spin_unlock_irqrestore(&uport->lock, flags);
return;
}
inline
void
set_connection_state(connection_state new_state) {
switch (new_state) {
case CONNECTED:
// configure carrier detect pin (DCD) to trigger on a rising edge
GICR &= ~_BV(INT2);
MCUCSR |= _BV(ISC2); // trigger on rising edge
GICR |= _BV(INT2);
GIFR |= _BV(INTF2);
STATUS_LED_PORT |= _BV(STATUS_LED);
break;
case DISCONNECTING:
set_dtr(false);
dtr_pulse_timer_ = DTR_PULSE_LENGTH;
break;
case DISCONNECTED:
// configure carrier detect pin (DCD) to trigger on a falling edge
GICR &= ~_BV(INT2);
MCUCSR &= ~_BV(ISC2); // trigger on falling edge
GICR |= _BV(INT2);
GIFR |= _BV(INTF2);
set_dtr(true);
STATUS_LED_PORT &= ~_BV(STATUS_LED);
break;
}
connection_state_ = new_state;
}
//-------------------------------------------------
// reset - reset channel status
//-------------------------------------------------
void z80sio_channel::device_reset()
{
LOG("%s\n", FUNCNAME);
// Reset RS232 emulation
receive_register_reset();
transmit_register_reset();
// disable receiver
m_wr3 &= ~WR3_RX_ENABLE;
// disable transmitter
m_wr5 &= ~WR5_TX_ENABLE;
m_rr0 |= RR0_TX_BUFFER_EMPTY;
m_rr1 |= RR1_ALL_SENT;
// reset external lines
set_rts(1);
set_dtr(1);
// reset interrupts
if (m_index == z80sio_device::CHANNEL_A)
{
m_uart->reset_interrupts();
}
}
static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
{
struct tegra_uart_port *tup = to_tegra_uport(u);
int dtr_enable;
tup->rts_active = !!(mctrl & TIOCM_RTS);
set_rts(tup, tup->rts_active);
dtr_enable = !!(mctrl & TIOCM_DTR);
set_dtr(tup, dtr_enable);
}
/* Sets io controls parameters */
static int ntty_tiocmset(struct tty_struct *tty,
unsigned int set, unsigned int clear)
{
struct nozomi *dc = get_dc_by_tty(tty);
unsigned long flags;
spin_lock_irqsave(&dc->spin_mutex, flags);
if (set & TIOCM_RTS)
set_rts(tty, 1);
else if (clear & TIOCM_RTS)
set_rts(tty, 0);
if (set & TIOCM_DTR)
set_dtr(tty, 1);
else if (clear & TIOCM_DTR)
set_dtr(tty, 0);
spin_unlock_irqrestore(&dc->spin_mutex, flags);
return 0;
}
/* Set the modem control signals state of uart controller. */
void tegra_uart_set_mctrl(struct uart_port *uport, unsigned int mctrl)
{
unsigned long flags;
struct tegra_uart_port *t;
t = container_of(uport, struct tegra_uart_port, uport);
spin_lock_irqsave(&uport->lock, flags);
if (mctrl & TIOCM_RTS) {
t->rts_active = true;
set_rts(t, true);
} else {
t->rts_active = false;
set_rts(t, false);
}
if (mctrl & TIOCM_DTR)
set_dtr(t, true);
else
set_dtr(t, false);
spin_unlock_irqrestore(&uport->lock, flags);
return;
}
static void tegra_set_mctrl(struct uart_port *u, unsigned int mctrl)
{
unsigned char mcr;
struct tegra_uart_port *t;
dev_dbg(u->dev, "tegra_set_mctrl called with %d\n", mctrl);
t = container_of(u, struct tegra_uart_port, uport);
mcr = t->mcr_shadow;
if (mctrl & TIOCM_RTS) {
t->rts_active = true;
set_rts(t, true);
} else {
t->rts_active = false;
set_rts(t, false);
}
if (mctrl & TIOCM_DTR)
set_dtr(t, true);
else
set_dtr(t, false);
return;
}
static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
{
struct tegra_uart_port *tup = to_tegra_uport(u);
unsigned long mcr;
int dtr_enable;
mcr = tup->mcr_shadow;
tup->rts_active = !!(mctrl & TIOCM_RTS);
set_rts(tup, tup->rts_active);
dtr_enable = !!(mctrl & TIOCM_DTR);
set_dtr(tup, dtr_enable);
return;
}
void z80sio_channel::update_rts()
{
// LOG("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index);
LOG("%s() \"%s\" Channel %c \n", FUNCNAME, m_owner->tag(), 'A' + m_index);
if (m_wr5 & WR5_RTS)
{
// when the RTS bit is set, the _RTS output goes low
set_rts(0);
m_rts = 1;
}
else
{
// when the RTS bit is reset, the _RTS output goes high after the transmitter empties
m_rts = 0;
}
// data terminal ready output follows the state programmed into the DTR bit*/
set_dtr((m_wr5 & WR5_DTR) ? 0 : 1);
}
void z80dart_channel::device_reset()
{
receive_register_reset();
transmit_register_reset();
// disable receiver
m_wr[3] &= ~WR3_RX_ENABLE;
// disable transmitter
m_wr[5] &= ~WR5_TX_ENABLE;
m_rr[0] |= RR0_TX_BUFFER_EMPTY;
// reset external lines
set_rts(1);
set_dtr(1);
// reset interrupts
if (m_index == z80dart_device::CHANNEL_A)
{
m_uart->reset_interrupts();
}
}
int do_serial_comms(const char *ttyfile, const char *baudrate, struct record *root)
{
int fd;
int len;
speed_t speed;
uint8_t *ptr;
struct record *rec;
const uint8_t BACKSPACE[] = {0x08};
const uint8_t ERASE_ALL[] = {0x00};
const uint8_t ACK = 0x06;
ptr = io_buffer;
if (baudrate_to_speed_t(baudrate, &speed)) {
fprintf(stderr, "unsupported baudrate, %s\n", baudrate);
return -1;
}
fd = serial_open(ttyfile, speed);
if (fd < 0) {
fprintf(stderr, "error opening serial port\n");
return -1;
}
fprintf(stdout, "Putting card into download mode.\n");
//Set PROG and reset
set_dtr(fd, true);
set_rts(fd, true);
sleep(1);
fprintf(stdout, "Trying to synchronize with ADuC70xx: ");
fflush(stdout);
while (serial_read_fully(fd, ptr, 1, 100));
set_rts(fd, false);
do {
len = serial_write_fully(fd, BACKSPACE, sizeof(BACKSPACE), 1000);
len = serial_read_fully(fd, ptr, 24, 100);
} while (!((len > 6) && (memcmp(ptr, "ADuC70", 6) == 0)));
//Disable PROG
set_dtr(fd, false);
while (serial_read_fully(fd, ptr, 1, 100));
if ((len > 6) && (memcmp(ptr, "ADuC70", 6) == 0)) {
int product_len = (memchr(ptr, ' ', 24) - (void *)ptr);
fprintf(stdout, "Found %.*s\n", product_len, ptr);
fprintf(stdout, "Erasing: ");
fflush(stdout);
len = fill_packet(ptr, 'E', 0x00000000, ERASE_ALL, sizeof(ERASE_ALL));
len = serial_write_fully(fd, ptr, len, 1000);
len = serial_read_fully(fd, ptr, 1, 10000);
if ((len <= 0) || (ptr[0] != ACK)) {
fprintf(stdout, "FAILED\n");
goto error;
}
fprintf(stdout, "OK\n");
rec = root;
while (rec != NULL) {
int count = 0;
uint32_t address = rec->address;
uint8_t *data = data_buffer;
struct record *drec;
for (drec = rec; ((drec != NULL) && ((address + count) == drec->address) && ((count + drec->count) < DATA_BUFFER_SIZE)); drec = drec->next) {
memcpy(data, drec->data, drec->count);
data += drec->count;
count += drec->count;
}
rec = drec;
fprintf(stdout, "Writting (%#x): ", address);
fflush(stdout);
len = fill_packet(ptr, 'W', address, data_buffer, count);
len = serial_write_fully(fd, ptr, len, 1000);
len = serial_read_fully(fd, ptr, 1, 10000);
if ((len <= 0) || (ptr[0] != ACK)) {
fprintf(stdout, "FAILED\n");
goto error;
}
fprintf(stdout, "OK\n");
}
if (reset) {
fprintf(stdout, "Resetting: ");
fflush(stdout);
len = fill_packet(ptr, 'R', 0x00000001, NULL, 0);
len = serial_write_fully(fd, ptr, len, 1000);
len = serial_read_fully(fd, ptr, 1, 10000);
if ((len <= 0) || (ptr[0] != ACK)) {
fprintf(stdout, "FAILED\n");
goto error;
}
fprintf(stdout, "OK\n");
}
} else {
fprintf(stdout, "FAILED\n");
goto error;
}
if (follow) {
int count = 600;
while (count--) {
len = serial_read(fd, ptr, 16, 1000);
if (len > 0) {
dump_text(stdout, ptr, len);
}
}
}
error:
if (serial_close(fd) < 0) {
fprintf(stderr, "error closing serial port\n");
return -1;
}
return 0;
}
void z80dart_channel::control_write(UINT8 data)
{
int reg = m_wr[0] & WR0_REGISTER_MASK;
LOG(("Z80DART \"%s\" Channel %c : Control Register Write '%02x'\n", m_owner->tag(), 'A' + m_index, data));
// write data to selected register
if (reg < 6)
m_wr[reg] = data;
if (reg != 0)
{
// mask out register index
m_wr[0] &= ~WR0_REGISTER_MASK;
}
switch (reg)
{
case 0:
switch (data & WR0_COMMAND_MASK)
{
case WR0_NULL:
LOG(("Z80DART \"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_SEND_ABORT:
LOG(("Z80DART \"%s\" Channel %c : Send Abort\n", m_owner->tag(), 'A' + m_index));
logerror("Z80DART \"%s\" Channel %c : unsupported command: Send Abort\n", m_owner->tag(), 'A' + m_index);
break;
case WR0_RESET_EXT_STATUS:
// reset external/status interrupt
m_rr[0] &= ~(RR0_DCD | RR0_RI | RR0_CTS | RR0_BREAK_ABORT);
if (!m_dcd) m_rr[0] |= RR0_DCD;
if (m_ri) m_rr[0] |= RR0_RI;
if (m_cts) m_rr[0] |= RR0_CTS;
m_rx_rr0_latch = 0;
LOG(("Z80DART \"%s\" Channel %c : Reset External/Status Interrupt\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_CHANNEL_RESET:
// channel reset
LOG(("Z80DART \"%s\" Channel %c : Channel Reset\n", m_owner->tag(), 'A' + m_index));
device_reset();
break;
case WR0_ENABLE_INT_NEXT_RX:
// enable interrupt on next receive character
LOG(("Z80DART \"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index));
m_rx_first = 1;
break;
case WR0_RESET_TX_INT:
// reset transmitter interrupt pending
LOG(("Z80DART \"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index));
logerror("Z80DART \"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index);
break;
case WR0_ERROR_RESET:
// error reset
LOG(("Z80DART \"%s\" Channel %c : Error Reset\n", m_owner->tag(), 'A' + m_index));
m_rr[1] &= ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR);
break;
case WR0_RETURN_FROM_INT:
// return from interrupt
LOG(("Z80DART \"%s\" Channel %c : Return from Interrupt\n", m_owner->tag(), 'A' + m_index));
m_uart->z80daisy_irq_reti();
break;
}
break;
case 1:
LOG(("Z80DART \"%s\" Channel %c : External Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Transmit Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Status Affects Vector %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait"));
LOG(("Z80DART \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit"));
switch (data & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_DISABLE:
LOG(("Z80DART \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index));
break;
case WR1_RX_INT_FIRST:
LOG(("Z80DART \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index));
break;
case WR1_RX_INT_ALL_PARITY:
LOG(("Z80DART \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index));
break;
case WR1_RX_INT_ALL:
LOG(("Z80DART \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index));
break;
}
m_uart->check_interrupts();
break;
case 2:
// interrupt vector
if (m_index == z80dart_device::CHANNEL_B)
m_rr[2] = ( m_rr[2] & 0x0e ) | ( m_wr[2] & 0xF1);;
m_uart->check_interrupts();
LOG(("Z80DART \"%s\" Channel %c : Interrupt Vector %02x\n", m_owner->tag(), 'A' + m_index, data));
break;
case 3:
LOG(("Z80DART \"%s\" Channel %c : Receiver Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Auto Enables %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Receiver Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_rx_word_length()));
update_serial();
break;
case 4:
LOG(("Z80DART \"%s\" Channel %c : Parity Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Parity %s\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd"));
LOG(("Z80DART \"%s\" Channel %c : Stop Bits %s\n", m_owner->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits())));
LOG(("Z80DART \"%s\" Channel %c : Clock Mode %uX\n", m_owner->tag(), 'A' + m_index, get_clock_mode()));
update_serial();
break;
case 5:
LOG(("Z80DART \"%s\" Channel %c : Transmitter Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Transmitter Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_tx_word_length()));
LOG(("Z80DART \"%s\" Channel %c : Send Break %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Request to Send %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0));
LOG(("Z80DART \"%s\" Channel %c : Data Terminal Ready %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0));
update_serial();
if (data & WR5_RTS)
{
// when the RTS bit is set, the _RTS output goes low
set_rts(0);
m_rts = 1;
}
else
{
// when the RTS bit is reset, the _RTS output goes high after the transmitter empties
m_rts = 0;
}
// data terminal ready output follows the state programmed into the DTR bit*/
set_dtr((data & WR5_DTR) ? 0 : 1);
break;
case 6:
LOG(("Z80DART \"%s\" Channel %c : Transmit Sync %02x\n", m_owner->tag(), 'A' + m_index, data));
m_sync = (m_sync & 0xff00) | data;
break;
case 7:
LOG(("Z80DART \"%s\" Channel %c : Receive Sync %02x\n", m_owner->tag(), 'A' + m_index, data));
m_sync = (data << 8) | (m_sync & 0xff);
break;
}
}
void ptt_serial_unix::set_tx(int tx) {
state_ = !!tx;
set_rts(state_);
set_dtr(state_);
}
void ptt_serial_windows::set_tx(int tx) {
state_ = !!tx;
set_rts(state_);
set_dtr(state_);
}
