void vpr_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch arch, INP t_options options) { /* Startup X graphics */ set_graphics_state(vpr_setup.ShowGraphics, vpr_setup.GraphPause, vpr_setup.RouterOpts.route_type); if (vpr_setup.ShowGraphics) { init_graphics("VPR: Versatile Place and Route for FPGAs", WHITE); alloc_draw_structs(); } /* Do placement and routing */ //bug here need to debug - corrected place_and_route(vpr_setup.Operation, vpr_setup.PlacerOpts, &vpr_setup.FileNameOpts, vpr_setup.AnnealSched, vpr_setup.RouterOpts, vpr_setup.RoutingArch, vpr_setup.Segments, vpr_setup.Timing, arch.Chans, arch.models, arch.Directs, arch.num_directs, &arch); //added QT - for main.c hunk 3 qt if(options.Count[OT_INC_DUMP_NETS]) { inc_dump_nets(&vpr_setup.FileNameOpts); } fflush(stdout); /* Close down X Display */ if (vpr_setup.ShowGraphics) close_graphics(); free_draw_structs(); }
int main(int argc, char **argv) { int simSize = 14; int xx; simResults = (double *) malloc(simSize*sizeof(double)); simCounts = (unsigned long *) malloc(simSize*sizeof(unsigned long)); simIndex = 0; for(xx = 0; xx < simSize ; xx++) { simResults[xx] = 0.0; simCounts[xx] = 0; } t_options Options; t_arch Arch = { 0 }; enum e_operation Operation; struct s_placer_opts PlacerOpts; struct s_annealing_sched AnnealSched; struct s_router_opts RouterOpts; struct s_det_routing_arch RoutingArch; t_segment_inf *Segments; t_timing_inf Timing; t_subblock_data Subblocks; boolean ShowGraphics; boolean TimingEnabled; int GraphPause; /* Print title message */ PrintTitle(); /* Print usage message if no args */ if(argc < 2) { PrintUsage(); exit(1); } /* Read in available inputs */ ReadOptions(argc, argv, &Options); /* Determine whether timing is on or off */ TimingEnabled = IsTimingEnabled(Options); /* Use inputs to configure VPR */ SetupVPR(Options, TimingEnabled, &Arch, &Operation, &PlacerOpts, &AnnealSched, &RouterOpts, &RoutingArch, &Segments, &Timing, &Subblocks, &ShowGraphics, &GraphPause); /* Check inputs are reasonable */ CheckOptions(Options, TimingEnabled); CheckArch(Arch, TimingEnabled); /* Verify settings don't conflict or otherwise not make sense */ CheckSetup(Operation, PlacerOpts, AnnealSched, RouterOpts, RoutingArch, Segments, Timing, Subblocks, Arch.Chans); /* Output the current settings to console. */ ShowSetup(Options, Arch, TimingEnabled, Operation, PlacerOpts, AnnealSched, RouterOpts, RoutingArch, Segments, Timing, Subblocks); if(Operation == TIMING_ANALYSIS_ONLY) { do_constant_net_delay_timing_analysis( Timing, Subblocks, Options.constant_net_delay); return 0; } /* Startup X graphics */ set_graphics_state(ShowGraphics, GraphPause, RouterOpts.route_type); if(ShowGraphics) { init_graphics("VPR: Versatile Place and Route for FPGAs"); alloc_draw_structs(); } /* Do the actual operation */ place_and_route(Operation, PlacerOpts, Options.PlaceFile, Options.NetFile, Options.ArchFile, Options.RouteFile, AnnealSched, RouterOpts, RoutingArch, Segments, Timing, &Subblocks, Arch.Chans); /* Close down X Display */ if(ShowGraphics) close_graphics(); /* free data structures */ free(Options.PlaceFile); free(Options.NetFile); free(Options.ArchFile); free(Options.RouteFile); freeArch(&Arch); printf("\nTiming Results\n"); for(xx = 0; xx < simSize ; xx++) { if(simCounts[xx] != 0) { simResults[xx] /= (double) simCounts[xx]; } printf("Index: %d\tAverage Clock: %f\n", xx, simResults[xx]); } free(simResults); free(simCounts); /* Return 0 to single success to scripts */ return 0; }
int main (int argc, char *argv[]) { #ifndef SPEC char title[] = "\n\nVPR FPGA Placement and Routing Program Version 4.22 " "by V. Betz.\n" "Source completed Jan. 25, 1999; compiled " __DATE__ ".\n" "This code is licensed only for non-commercial use.\n\n"; #else char title[] = "\n\nVPR FPGA Placement and Routing Program Version 4.00-spec" "\nSource completed Sept. 19, 1997.\n\n"; #endif char net_file[BUFSIZE], place_file[BUFSIZE], arch_file[BUFSIZE]; char route_file[BUFSIZE]; float aspect_ratio; boolean full_stats, user_sized; char pad_loc_file[BUFSIZE]; enum e_operation operation; boolean verify_binary_search; boolean show_graphics; int gr_automode; struct s_annealing_sched annealing_sched; struct s_placer_opts placer_opts; struct s_router_opts router_opts; struct s_det_routing_arch det_routing_arch; t_segment_inf *segment_inf; t_timing_inf timing_inf; t_subblock_data subblock_data; t_chan_width_dist chan_width_dist; float constant_net_delay; printf("%s",title); placer_opts.pad_loc_file = pad_loc_file; /* Parse the command line. */ parse_command (argc, argv, net_file, arch_file, place_file, route_file, &operation, &aspect_ratio, &full_stats, &user_sized, &verify_binary_search, &gr_automode, &show_graphics, &annealing_sched, &placer_opts, &router_opts, &timing_inf.timing_analysis_enabled, &constant_net_delay); /* Parse input circuit and architecture */ get_input (net_file, arch_file, placer_opts.place_cost_type, placer_opts.num_regions, aspect_ratio, user_sized, router_opts.route_type, &det_routing_arch, &segment_inf, &timing_inf, &subblock_data, &chan_width_dist); if (full_stats == TRUE) print_lambda (); #ifdef DEBUG print_netlist ("net.echo", net_file, subblock_data); print_arch (arch_file, router_opts.route_type, det_routing_arch, segment_inf, timing_inf, subblock_data, chan_width_dist); #endif if (operation == TIMING_ANALYSIS_ONLY) { /* Just run the timing analyzer. */ do_constant_net_delay_timing_analysis (timing_inf, subblock_data, constant_net_delay); free_subblock_data (&subblock_data); exit (0); } set_graphics_state (show_graphics, gr_automode, router_opts.route_type); if (show_graphics) { /* Get graphics going */ init_graphics("VPR: Versatile Place and Route for FPGAs"); alloc_draw_structs (); } fflush (stdout); place_and_route (operation, placer_opts, place_file, net_file, arch_file, route_file, full_stats, verify_binary_search, annealing_sched, router_opts, det_routing_arch, segment_inf, timing_inf, &subblock_data, chan_width_dist); if (show_graphics) close_graphics(); /* Close down X Display */ exit (0); }