/*-------------------------------------------------------------------*/ int ARCH_DEP(initial_cpu_reset) (REGS *regs) { /* Clear reset pending indicators */ regs->sigpireset = regs->sigpreset = 0; /* Clear the registers */ memset ( ®s->psw, 0, sizeof(regs->psw) ); memset ( ®s->captured_zpsw, 0, sizeof(regs->captured_zpsw) ); memset ( regs->cr, 0, sizeof(regs->cr) ); regs->fpc = 0; regs->PX = 0; regs->psw.AMASK_G = AMASK24; /* * ISW20060125 : Since we reset the prefix, we must also adjust * the PSA ptr */ regs->psa = (PSA_3XX *)regs->mainstor; /* Perform a CPU reset (after setting PSA) */ ARCH_DEP(cpu_reset) (regs); regs->todpr = 0; regs->clkc = 0; set_cpu_timer(regs, 0); #ifdef _FEATURE_INTERVAL_TIMER set_int_timer(regs, 0); #endif /* The breaking event address register is initialised to 1 */ regs->bear = 1; /* Initialize external interrupt masks in control register 0 */ regs->CR(0) = CR0_XM_ITIMER | CR0_XM_INTKEY | CR0_XM_EXTSIG; #ifdef FEATURE_S370_CHANNEL /* For S/370 initialize the channel masks in CR2 */ regs->CR(2) = 0xFFFFFFFF; #endif /*FEATURE_S370_CHANNEL*/ regs->chanset = #if defined(FEATURE_CHANNEL_SWITCHING) regs->cpuad < FEATURE_LCSS_MAX ? regs->cpuad : #endif /*defined(FEATURE_CHANNEL_SWITCHING)*/ 0xFFFF; /* Initialize the machine check masks in control register 14 */ regs->CR(14) = CR14_CHKSTOP | CR14_SYNCMCEL | CR14_XDMGRPT; #ifndef FEATURE_LINKAGE_STACK /* For S/370 initialize the MCEL address in CR15 */ regs->CR(15) = 512; #endif /*!FEATURE_LINKAGE_STACK*/ if(regs->host && regs->guestregs) ARCH_DEP(initial_cpu_reset)(regs->guestregs); return 0; } /* end function initial_cpu_reset */
/*-------------------------------------------------------------------*/ int ARCH_DEP(initial_cpu_reset) (REGS *regs) { int rc1 = 0, rc; /* Clear reset pending indicators */ regs->sigpireset = regs->sigpreset = 0; /* Clear the registers */ memset ( ®s->psw, 0, sizeof(regs->psw) ); memset ( ®s->captured_zpsw, 0, sizeof(regs->captured_zpsw) ); #ifndef NOCHECK_AEA_ARRAY_BOUNDS memset ( ®s->cr_struct, 0, sizeof(regs->cr_struct) ); #else memset ( ®s->cr, 0, sizeof(regs->cr) ); #endif regs->fpc = 0; regs->PX = 0; regs->psw.AMASK_G = AMASK24; /* Ensure memory sizes are properly indicated */ regs->mainstor = sysblk.mainstor; regs->storkeys = sysblk.storkeys; regs->mainlim = sysblk.mainsize ? (sysblk.mainsize - 1) : 0; regs->psa = (PSA_3XX*)regs->mainstor; /* Perform a CPU reset (after setting PSA) */ rc1 = ARCH_DEP(cpu_reset) (regs); regs->todpr = 0; regs->clkc = 0; set_cpu_timer(regs, 0); #ifdef _FEATURE_INTERVAL_TIMER set_int_timer(regs, 0); #endif /* The breaking event address register is initialised to 1 */ regs->bear = 1; /* Initialize external interrupt masks in control register 0 */ regs->CR(0) = CR0_XM_INTKEY | CR0_XM_EXTSIG | (FACILITY_ENABLED(INTERVAL_TIMER, regs) ? CR0_XM_ITIMER : 0); #if defined(FEATURE_S370_CHANNEL) && !defined(FEATURE_ACCESS_REGISTERS) /* For S/370 initialize the channel masks in CR2 */ regs->CR(2) = 0xFFFFFFFF; #endif /* defined(FEATURE_S370_CHANNEL) && !defined(FEATURE_ACCESS_REGISTERS) */ regs->chanset = #if defined(FEATURE_CHANNEL_SWITCHING) regs->cpuad < FEATURE_LCSS_MAX ? regs->cpuad : #endif /*defined(FEATURE_CHANNEL_SWITCHING)*/ 0xFFFF; /* Initialize the machine check masks in control register 14 */ regs->CR(14) = CR14_CHKSTOP | CR14_SYNCMCEL | CR14_XDMGRPT; #ifndef FEATURE_LINKAGE_STACK /* For S/370 initialize the MCEL address in CR15 */ regs->CR(15) = 512; #endif /*!FEATURE_LINKAGE_STACK*/ if(regs->host && regs->guestregs) if( (rc = ARCH_DEP(initial_cpu_reset)(regs->guestregs)) ) rc1 = rc; #ifdef FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_3 renew_wrapping_keys(); #endif /* FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_3 */ return rc1; } /* end function initial_cpu_reset */