static int gk20a_clk_export_enable(void *data)
{
int ret;
struct gk20a *g = data;
struct clk_gk20a *clk = &g->clk;
mutex_lock(&clk->clk_mutex);
ret = set_pll_freq(g, clk->gpc_pll.freq, clk->gpc_pll.freq);
mutex_unlock(&clk->clk_mutex);
return ret;
}
static int gk20a_init_clk_support(struct gk20a *g)
{
struct clk_gk20a *clk = &g->clk;
u32 err;
gk20a_dbg_fn("");
clk->g = g;
err = gk20a_init_clk_reset_enable_hw(g);
if (err)
return err;
err = gk20a_init_clk_setup_sw(g);
if (err)
return err;
mutex_lock(&clk->clk_mutex);
clk->clk_hw_on = true;
err = gk20a_init_clk_setup_hw(g);
mutex_unlock(&clk->clk_mutex);
if (err)
return err;
err = gk20a_clk_register_export_ops(g);
if (err)
return err;
/* FIXME: this effectively prevents host level clock gating */
err = clk_enable(g->clk.tegra_clk);
if (err)
return err;
/* The prev call may not enable PLL if gbus is unbalanced - force it */
mutex_lock(&clk->clk_mutex);
err = set_pll_freq(g, clk->gpc_pll.freq, clk->gpc_pll.freq);
mutex_unlock(&clk->clk_mutex);
if (err)
return err;
#ifdef CONFIG_DEBUG_FS
if (!clk->debugfs_set) {
if (!clk_gk20a_debugfs_init(g))
clk->debugfs_set = true;
}
#endif
return err;
}
int gk20a_init_clk_support(struct gk20a *g)
{
struct clk_gk20a *clk = &g->clk;
u32 err;
nvhost_dbg_fn("");
clk->g = g;
err = gk20a_init_clk_reset_enable_hw(g);
if (err)
return err;
err = gk20a_init_clk_setup_sw(g);
if (err)
return err;
mutex_lock(&clk->clk_mutex);
clk->clk_hw_on = true;
err = gk20a_init_clk_setup_hw(g);
mutex_unlock(&clk->clk_mutex);
if (err)
return err;
err = gk20a_clk_register_export_ops(g);
if (err)
return err;
/* FIXME: this effectively prevents host level clock gating */
err = clk_enable(g->clk.tegra_clk);
if (err)
return err;
/* The prev call may not enable PLL if gbus is unbalanced - force it */
mutex_lock(&clk->clk_mutex);
err = set_pll_freq(g, clk->gpc_pll.freq, clk->gpc_pll.freq);
mutex_unlock(&clk->clk_mutex);
if (err)
return err;
gk20a_writel(g,
timer_pri_timeout_r(),
timer_pri_timeout_period_f(0x200) |
timer_pri_timeout_en_m());
return err;
}
static int gk20a_clk_export_set_rate(void *data, unsigned long *rate)
{
u32 old_freq;
int ret = -ENODATA;
struct gk20a *g = data;
struct clk_gk20a *clk = &g->clk;
if (rate) {
mutex_lock(&clk->clk_mutex);
old_freq = clk->gpc_pll.freq;
ret = set_pll_target(g, rate_gpu_to_gpc2clk(*rate), old_freq);
if (!ret && clk->gpc_pll.enabled)
ret = set_pll_freq(g, clk->gpc_pll.freq, old_freq);
if (!ret)
*rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
mutex_unlock(&clk->clk_mutex);
}
return ret;
}
