예제 #1
0
void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
		const struct emif_regs *regs,
		const struct dmm_lisa_map_regs *lisa_regs, int nrs)
{
	int i;

	enable_emif_clocks();

	for (i = 0; i < nrs; i++)
		ddr_init_settings(ctrl, i);

	enable_dmm_clocks();

	/* Program the DMM to for non-interleaved configuration */
	config_dmm(lisa_regs);

	/* Program EMIF CFG Registers */
	for (i = 0; i < nrs; i++) {
		set_sdram_timings(regs, i);
		config_sdram(regs, i);
	}

	udelay(1000);
	for (i = 0; i < nrs; i++)
		ddr3_sw_levelling(data, i);

	udelay(50000);	/* Some delay needed */
}
예제 #2
0
void config_ddr(short ddr_type)
{
	int ddr_pll, ioctrl_val;
	const struct emif_regs *emif_regs;
	const struct ddr_data *ddr_data;
	const struct cmd_control *cmd_ctrl_data;

	if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
		ddr_pll = 266;
		cmd_ctrl_data = &ddr2_cmd_ctrl_data;
		ddr_data = &ddr2_data;
		ioctrl_val = DDR2_IOCTRL_VALUE;
		emif_regs = &ddr2_emif_reg_data;
	} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
		ddr_pll = 303;
		ioctrl_val = DDR3_IOCTRL_VALUE;
		cmd_ctrl_data = &ddr3_cmd_ctrl_data;
		if (board_is_evm_15_or_later()) {
			ddr_data = &ddr3_evm_data;
			emif_regs = &ddr3_evm_emif_reg_data;
		} else {
			ddr_data = &ddr3_data;
			emif_regs = &ddr3_emif_reg_data;
		}
	} else {
		puts("Unknown memory type");
		hang();
	}

	enable_emif_clocks();
	ddr_pll_config(ddr_pll);
	config_vtp();
	config_cmd_ctrl(cmd_ctrl_data);

	config_ddr_data(0, ddr_data);
	config_ddr_data(1, ddr_data);

	config_io_ctrl(ioctrl_val);

	/* Set CKE to be controlled by EMIF/DDR PHY */
	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);

	/* Program EMIF instance */
	config_ddr_phy(emif_regs);
	set_sdram_timings(emif_regs);
	config_sdram(emif_regs);
}
예제 #3
0
파일: emif4.c 프로젝트: ehamine/u-boot
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
                const struct ddr_data *data, const struct cmd_control *ctrl,
                const struct emif_regs *regs, int nr)
{
    ddr_pll_config(pll);
#ifndef CONFIG_TI816X
    config_vtp(nr);
#endif
    config_cmd_ctrl(ctrl, nr);

    config_ddr_data(data, nr);
#ifdef CONFIG_AM33XX
    config_io_ctrl(ioregs);

    /* Set CKE to be controlled by EMIF/DDR PHY */
    writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);

#endif
#ifdef CONFIG_AM43XX
    writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
    while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
        ;

    config_io_ctrl(ioregs);

    /* Set CKE to be controlled by EMIF/DDR PHY */
    writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);

    /* Allow EMIF to control DDR_RESET */
    writel(0x00000000, &ddrctrl->ddrioctrl);
#endif

    /* Program EMIF instance */
    config_ddr_phy(regs, nr);
    set_sdram_timings(regs, nr);
    if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
        config_sdram_emif4d5(regs, nr);
    else
        config_sdram(regs, nr);
}
예제 #4
0
void config_ddr(unsigned int pll, unsigned int ioctrl,
		const struct ddr_data *data, const struct cmd_control *ctrl,
		const struct emif_regs *regs)
{
	enable_emif_clocks();
	ddr_pll_config(pll);
	config_vtp();
	config_cmd_ctrl(ctrl);

	config_ddr_data(0, data);
	config_ddr_data(1, data);

	config_io_ctrl(ioctrl);

	/* Set CKE to be controlled by EMIF/DDR PHY */
	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);

	/* Program EMIF instance */
	config_ddr_phy(regs);
	set_sdram_timings(regs);
	config_sdram(regs);
}