static void init_pa10_pxx() { INTERNAL_RF_ON(); // Timer1, channel 3 setupPulsesPXX(INTERNAL_MODULE) ; // TODO not here! // RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock GPIO_InitTypeDef GPIO_InitStructure; RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_INTPPM, ENABLE); GPIO_PinAFConfig(GPIO_INTPPM, GPIO_PinSource_INTPPM, GPIO_AF_TIM1); GPIO_InitStructure.GPIO_Pin = PIN_INTPPM_OUT; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIO_INTPPM, &GPIO_InitStructure); RCC->APB2ENR |= RCC_APB2ENR_TIM1EN ; // Enable clock RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock TIM1->CR1 &= ~TIM_CR1_CEN ; TIM1->ARR = 18000 ; // 9mS TIM1->CCR2 = 15000 ; // Update time TIM1->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz TIM1->CCER = TIM_CCER_CC3E ; TIM1->CR2 = TIM_CR2_OIS3 ; // O/P idle high TIM1->BDTR = TIM_BDTR_MOE ; // Enable outputs TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0]; TIM1->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high TIM1->EGR = 1 ; // Restart // TIM1->SR &= ~TIM_SR_UIF ; // Clear flag // TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag TIM1->DIER |= TIM_DIER_CC3DE ; // Enable DMA on CC3 match TIM1->DCR = 15 ; // DMA to CC1 // TIM1->CR1 = TIM_CR1_OPM ; // Just run once // Enable the DMA channel here, DMA2 stream 6, channel 6 DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; DMA2_Stream6->PAR = CONVERT_PTR_UINT(&TIM1->DMAR); DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&pxxStream[INTERNAL_MODULE][1]); // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->NDTR = 100 ; DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA TIM1->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM1->CR1 |= TIM_CR1_CEN ; NVIC_EnableIRQ(TIM1_CC_IRQn); NVIC_SetPriority(TIM1_CC_IRQn, 7); }
static void init_pa7_pxx() { EXTERNAL_RF_ON(); // Timer8 setupPulsesPXX(EXTERNAL_MODULE); RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock #if defined(REV3) configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ; #else configure_pins( PIN_EXTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25 | PIN_PUSHPULL ) ; #endif RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock TIM8->CR1 &= ~TIM_CR1_CEN ; TIM8->ARR = 18000 ; // 9mS TIM8->CCR2 = 15000 ; // Update time TIM8->PSC = (PeripheralSpeeds.Peri2_frequency * PeripheralSpeeds.Timer_mult2) / 2000000 - 1 ; // 0.5uS from 30MHz #if defined(REV3) TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ; #else #ifdef PCB9XT TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ; #else TIM8->CCER = TIM_CCER_CC1NE ; #endif #endif TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0] ; TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high TIM8->EGR = 1 ; // Restart // TIM8->SR &= ~TIM_SR_UIF ; // Clear flag // TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag TIM8->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match TIM8->DCR = 13 ; // DMA to CC1 // TIM8->CR1 = TIM_CR1_OPM ; // Just run once // Enable the DMA channel here, DMA2 stream 2, channel 7 DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; DMA2_Stream2->PAR = CONVERT_PTR(&TIM8->DMAR); DMA2_Stream2->M0AR = CONVERT_PTR(&pxxStream[EXTERNAL_MODULE][1]); // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->NDTR = 100 ; DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM8->CR1 |= TIM_CR1_CEN ; NVIC_SetPriority( TIM8_CC_IRQn, 3 ) ; // Lower priority interrupt NVIC_EnableIRQ(TIM8_CC_IRQn) ; }
static void init_pa10_pxx() { INTERNAL_RF_ON(); // Timer1, channel 3 setupPulsesPXX(0) ; // TODO not here! RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_INTPPM, ENABLE); configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ; RCC->APB2ENR |= RCC_APB2ENR_TIM1EN ; // Enable clock RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock TIM1->CR1 &= ~TIM_CR1_CEN ; TIM1->ARR = 18000 ; // 9mS TIM1->CCR2 = 15000 ; // Update time TIM1->PSC = (PeripheralSpeeds.Peri2_frequency * PeripheralSpeeds.Timer_mult2) / 2000000 - 1 ; // 0.5uS from 30MHz TIM1->CCER = TIM_CCER_CC3E ; TIM1->CR2 = TIM_CR2_OIS3 ; // O/P idle high TIM1->BDTR = TIM_BDTR_MOE ; // Enable outputs TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0]; TIM1->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high TIM1->EGR = 1 ; // Restart // TIM1->SR &= ~TIM_SR_UIF ; // Clear flag // TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA TIM1->DIER |= TIM_DIER_CC3DE ; // Enable DMA on CC3 match TIM1->DCR = 15 ; // DMA to CC1 // TIM1->CR1 = TIM_CR1_OPM ; // Just run once // Enable the DMA channel here, DMA2 stream 6, channel 6 DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; DMA2_Stream6->PAR = CONVERT_PTR(&TIM1->DMAR); DMA2_Stream6->M0AR = CONVERT_PTR(&pxxStream[INTERNAL_MODULE][1]); // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->NDTR = 100 ; DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA TIM1->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM1->CR1 |= TIM_CR1_CEN ; NVIC_SetPriority( TIM1_CC_IRQn, 3 ) ; // Lower priority interrupt NVIC_EnableIRQ(TIM1_CC_IRQn) ; }
void extmodulePxxStart() { EXTERNAL_MODULE_ON(); // Timer8 setupPulsesPXX(EXTERNAL_MODULE); GPIO_InitTypeDef GPIO_InitStructure; GPIO_PinAFConfig(EXTMODULE_GPIO, EXTMODULE_GPIO_PinSource, EXTMODULE_GPIO_AF); GPIO_InitStructure.GPIO_Pin = EXTMODULE_GPIO_PIN; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(EXTMODULE_GPIO, &GPIO_InitStructure); EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ; EXTMODULE_TIMER->ARR = 18000 ; // 9mS EXTMODULE_TIMER->CCR2 = 15000 ; // Update time EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE ; EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1 ; // O/P idle high EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0]; EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high EXTMODULE_TIMER->EGR = 1 ; // Restart EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match EXTMODULE_TIMER->DCR = 13 ; // DMA to CC1 // Enable the DMA channel here, DMA2 stream 2, channel 7 DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; DMA2_Stream2->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->DMAR); DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]); // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->NDTR = 100 ; DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ; NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ; NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); }
static void intmodulePxxStart() { INTERNAL_MODULE_ON(); // Timer1, channel 3 setupPulsesPXX(INTERNAL_MODULE) ; // TODO not here! GPIO_InitTypeDef GPIO_InitStructure; GPIO_PinAFConfig(INTMODULE_GPIO, INTMODULE_GPIO_PinSource, INTMODULE_GPIO_AF); GPIO_InitStructure.GPIO_Pin = INTMODULE_GPIO_PIN; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(INTMODULE_GPIO, &GPIO_InitStructure); INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ; INTMODULE_TIMER->ARR = 18000 ; // 9mS INTMODULE_TIMER->CCR2 = 15000 ; // Update time INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz INTMODULE_TIMER->CCER = TIM_CCER_CC3E ; INTMODULE_TIMER->CR2 = TIM_CR2_OIS3 ; // O/P idle high INTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs INTMODULE_TIMER->CCR3 = modulePulsesData[INTERNAL_MODULE].pxx.pulses[0]; INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high INTMODULE_TIMER->EGR = 1 ; // Restart INTMODULE_TIMER->DIER |= TIM_DIER_CC3DE ; // Enable DMA on CC3 match INTMODULE_TIMER->DCR = 15 ; // DMA to CC1 // Enable the DMA channel here, DMA2 stream 6, channel 6 DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; DMA2_Stream6->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->DMAR); DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&modulePulsesData[INTERNAL_MODULE].pxx.pulses[1]); DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt INTMODULE_TIMER->CR1 |= TIM_CR1_CEN ; NVIC_EnableIRQ(TIM1_CC_IRQn); NVIC_SetPriority(TIM1_CC_IRQn, 7); }
void setupPulses(unsigned int port) { heartbeat |= HEART_TIMER_PULSES ; #ifdef REV9E SuCount += 1 ; // progress( 0xA000 + port + ( SuCount << 4 ) ) ; // return ; #endif if ( port == 0 ) { if ( s_current_protocol[0] != g_model.protocol ) { switch( s_current_protocol[0] ) { // stop existing protocol hardware case PROTO_PPM: disable_main_ppm() ; break; case PROTO_PXX: disable_pxx(0) ; break; // case PROTO_DSM2: // disable_ssc() ; // break; // case PROTO_PPM16 : // disable_main_ppm() ; // break ; } s_current_protocol[0] = g_model.protocol ; switch(s_current_protocol[0]) { // Start new protocol hardware here case PROTO_PPM: init_main_ppm() ; break; case PROTO_PXX: init_pxx(0) ; break; case PROTO_OFF: init_no_pulses( INTERNAL_MODULE ) ; break; // case PROTO_DSM2: // init_main_ppm( 5000, 0 ) ; // Initial period 2.5 mS, output off // init_ssc() ; // break; // case PROTO_PPM16 : // init_main_ppm( 3000, 1 ) ; // Initial period 1.5 mS, output on // break ; } } // Set up output data here switch(s_current_protocol[0]) { case PROTO_PPM: setupPulsesPpm(); // Don't enable interrupts through here break; case PROTO_PXX: setupPulsesPXX(0); break; // case PROTO_DSM2: //// sei() ; // Interrupts allowed here // setupPulsesDsm2(6); // break; // case PROTO_PPM16 : // setupPulsesPPM(); // Don't enable interrupts through here //// // PPM16 pulses are set up automatically within the interrupts //// break ; } } else { if ( s_current_protocol[1] != g_model.xprotocol ) { switch( s_current_protocol[1] ) { // stop existing protocol hardware case PROTO_PPM: disable_ppm(EXTERNAL_MODULE) ; break; case PROTO_PXX: disable_pxx(EXTERNAL_MODULE) ; break; case PROTO_DSM2: disable_dsm2(EXTERNAL_MODULE) ; break; #ifdef ASSAN case PROTO_ASSAN : disable_assan(EXTERNAL_MODULE) ; break; #endif // case PROTO_PPM16 : // disable_main_ppm() ; // break ; } s_current_protocol[1] = g_model.xprotocol ; switch(s_current_protocol[1]) { // Start new protocol hardware here case PROTO_PPM: setupPulsesPpmx() ; init_ppm(EXTERNAL_MODULE) ; break; case PROTO_PXX: init_pxx(EXTERNAL_MODULE) ; break; case PROTO_OFF: init_no_pulses( EXTERNAL_MODULE ) ; break; case PROTO_DSM2: init_dsm2(EXTERNAL_MODULE) ; break; #ifdef ASSAN case PROTO_ASSAN : init_assan(EXTERNAL_MODULE) ; break; #endif // case PROTO_PPM16 : // init_main_ppm( 3000, 1 ) ; // Initial period 1.5 mS, output on // break ; } } // Set up output data here switch(s_current_protocol[1]) { case PROTO_PPM: setupPulsesPpmx(); // Don't enable interrupts through here break; case PROTO_PXX: setupPulsesPXX(1); break; case PROTO_DSM2: // sei() ; // Interrupts allowed here setupPulsesDsm2(6); break; #ifdef ASSAN case PROTO_ASSAN : setupPulsesDsm2(g_model.xppmNCH) ; break; #endif // case PROTO_PPM16 : // setupPulsesPPM(); // Don't enable interrupts through here //// // PPM16 pulses are set up automatically within the interrupts //// break ; } } }
static void init_pa7_pxx() { EXTERNAL_RF_ON(); // Timer8 setupPulsesPXX(EXTERNAL_MODULE); RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock #if defined(REV3) configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ; #else GPIO_InitTypeDef GPIO_InitStructure; RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_EXTPPM, ENABLE); GPIO_PinAFConfig(GPIO_EXTPPM, GPIO_PinSource_EXTPPM, GPIO_AF_TIM8); GPIO_InitStructure.GPIO_Pin = PIN_EXTPPM_OUT; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIO_EXTPPM, &GPIO_InitStructure); #endif RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock TIM8->CR1 &= ~TIM_CR1_CEN ; TIM8->ARR = 18000 ; // 9mS TIM8->CCR2 = 15000 ; // Update time TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz #if defined(REV3) TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ; #else TIM8->CCER = TIM_CCER_CC1NE ; #endif TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0] ; TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high TIM8->EGR = 1 ; // Restart // TIM8->SR &= ~TIM_SR_UIF ; // Clear flag // TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag TIM8->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match TIM8->DCR = 13 ; // DMA to CC1 // TIM8->CR1 = TIM_CR1_OPM ; // Just run once // Enable the DMA channel here, DMA2 stream 2, channel 7 DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR); DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&pxxStream[EXTERNAL_MODULE][1]); // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->NDTR = 100 ; DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM8->CR1 |= TIM_CR1_CEN ; NVIC_EnableIRQ(TIM8_CC_IRQn) ; NVIC_SetPriority(TIM8_CC_IRQn, 7); }
void setupPulses() { uint8_t required_protocol ; required_protocol = g_model.protocol ; // Sort required_protocol depending on student mode and PPMSIM allowed if ( g_eeGeneral.enablePpmsim ) { if ( SlaveMode ) { required_protocol = PROTO_PPMSIM ; } } if ( PausePulses ) { required_protocol = PROTO_NONE ; } // SPY_ON; if ( Current_protocol != required_protocol ) { Current_protocol = required_protocol ; // switch mode here TCCR1B = 0 ; // Stop counter TCNT1 = 0 ; #ifdef CPUM2561 TIMSK1 &= ~( (1<<OCIE1A) | (1<<OCIE1B) | (1<<OCIE1C) | (1<<ICIE1) | (1<<TOIE1) ) ; // All interrupts off // TIMSK1 &= ~(1<<OCIE1C) ; // COMPC1 off TIFR1 = ( (1<<OCF1A) | (1<<OCF1B) | (1<<OCF1C) | (1<<ICF1) | (1<<TOV1) ) ; // Clear all pending interrupts TIFR3 = ( (1<<OCF3A) | (1<<OCF3B) | (1<<OCF3C) | (1<<ICF3) | (1<<TOV3) ) ; // Clear all pending interrupts #else TIMSK &= ~0x3C ; // All interrupts off ETIMSK &= ~(1<<OCIE1C) ; // COMPC1 off TIFR = 0x3C ; // Clear all pending interrupts ETIFR = 0x3F ; // Clear all pending interrupts #endif switch(required_protocol) { case PROTO_PPM: set_timer3_capture() ; setPpmTimers() ; break; case PROTO_PXX: set_timer3_capture() ; OCR1B = 7000 ; // Next frame starts in 3.5 mS OCR1C = 4000 ; // Next frame setup in 2 mS #ifdef CPUM2561 TIMSK1 |= (1<<OCIE1B) | (1<<OCIE1C); // Enable COMPB and COMPC #else TIMSK |= (1<<OCIE1B) ; // Enable COMPB ETIMSK |= (1<<OCIE1C); // Enable COMPC #endif TCCR1A = 0; TCCR1B = (2<<CS10); //ICNC3 16MHz / 8 break; #ifdef MULTI_PROTOCOL case PROTO_MULTI: #endif // MULTI_PROTOCOL #ifdef SBUS_PROTOCOL case PROTO_SBUS: #endif // SBUS_PROTOCOL case PROTO_DSM2: set_timer3_capture() ; OCR1C = 200 ; // 100 uS TCNT1 = 300 ; // Past the OCR1C value ICR1 = 44000 ; // Next frame starts in 11/22 mS #ifdef CPUM2561 TIMSK1 |= (1<<ICIE1) ; // Enable CAPT #else TIMSK |= (1<<TICIE1) ; // Enable CAPT #endif #ifdef CPUM2561 TIMSK1 |= (1<<OCIE1C); // Enable COMPC #else ETIMSK |= (1<<OCIE1C); // Enable COMPC #endif TCCR1A = (0<<WGM10) ; TCCR1B = (3 << WGM12) | (2<<CS10) ; // CTC ICR, 16MHz / 8 break; case PROTO_PPM16 : case PROTO_PPMSIM : if ( required_protocol == PROTO_PPMSIM ) { setupPulsesPPM(PROTO_PPMSIM); PORTB &= ~(1<<OUT_B_PPM); // Hold PPM output low } else { setPpmTimers() ; setupPulsesPPM(PROTO_PPM16); } OCR3A = 50000 ; OCR3B = 5000 ; set_timer3_ppm() ; break ; // case PROTO_PPMSIM : // setupPulsesPPM(PROTO_PPMSIM); // PORTB &= ~(1<<OUT_B_PPM); // Hold PPM output low // OCR3A = 50000 ; // OCR3B = 5000 ; // set_timer3_ppm() ; // break ; } } switch(required_protocol) { case PROTO_PPM: setupPulsesPPM( PROTO_PPM ); // Don't enable interrupts through here break; case PROTO_PXX: sei() ; // Interrupts allowed here setupPulsesPXX(); break; #ifdef MULTI_PROTOCOL case PROTO_MULTI: #endif // MULTI_PROTOCOL #ifdef SBUS_PROTOCOL case PROTO_SBUS: #endif // SBUS_PROTOCOL case PROTO_DSM2: sei() ; // Interrupts allowed here setupPulsesSerial(); break; case PROTO_PPM16 : setupPulsesPPM( PROTO_PPM ); // Don't enable interrupts through here // PPM16 pulses are set up automatically within the interrupts break ; } // SPY_OFF; //extern void nothing() ; // nothing() ; asm("") ; }