int __init arch_clk_init(void) { int k, ret = 0; /* autodetect extal or fll configuration */ if (__raw_readl(PLLCR) & 0x1000) pll_clk.parent = &fll_clk; else pll_clk.parent = &extal_clk; for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); return ret; }
int __init arch_clk_init(void) { int k, ret = 0; /* */ if (__raw_readl(PLLCR) & 0x1000) pll_clk.parent = &dll_clk; else pll_clk.parent = &extal_clk; for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); return ret; }
void __init r8a7740_clock_init(u8 md_ck) { int k, ret = 0; /* detect system clock parent */ if (md_ck & MD_CK1) system_clk.parent = &extal1_div2_clk; else system_clk.parent = &extal1_clk; /* detect RCLK parent */ switch (md_ck & (MD_CK2 | MD_CK1)) { case MD_CK2 | MD_CK1: r_clk.parent = &extal1_div2048_clk; break; case MD_CK2: r_clk.parent = &extal1_div1024_clk; break; case MD_CK1: default: r_clk.parent = &extalr_clk; break; } for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR); if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) ret = clk_register(late_main_clks[k]); if (!ret) ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) shmobile_clk_init(); else panic("failed to setup r8a7740 clocks\n"); }
void __init r8a7790_clock_init(void) { u32 mode = rcar_gen2_read_mode_pins(); int k, ret = 0; switch (mode & (MD(14) | MD(13))) { case 0: R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); break; case MD(13): R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); break; case MD(14): R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102); break; case MD(13) | MD(14): R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88); break; } if (mode & (MD(18))) SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36); else SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24); if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2)) SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16); else SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20); for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) shmobile_clk_init(); else panic("failed to setup r8a7790 clocks\n"); }
void __init sh7377_clock_init(void) { int k, ret = 0; for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); if (!ret) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) shmobile_clk_init(); else panic("failed to setup sh7377 clocks\n"); }