static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) { int port = eth->port, ret = 0; u32 val; struct sh_eth_info *port_info = ð->port_info[port]; struct eth_device *dev = port_info->dev; struct phy_device *phy; /* Configure e-dmac registers */ sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL, EDMR); sh_eth_write(eth, 0, EESIPR); sh_eth_write(eth, 0, TRSCER); sh_eth_write(eth, 0, TFTR); sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); sh_eth_write(eth, RMCR_RST, RMCR); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, 0, RPADIR); #endif sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); /* Configure e-mac registers */ sh_eth_write(eth, 0, ECSIPR); /* Set Mac address */ val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | dev->enetaddr[2] << 8 | dev->enetaddr[3]; sh_eth_write(eth, val, MAHR); val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; sh_eth_write(eth, val, MALR); sh_eth_write(eth, RFLR_RFL_MIN, RFLR); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, 0, PIPR); sh_eth_write(eth, APR_AP, APR); sh_eth_write(eth, MPR_MP, MPR); sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); #endif #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); #endif /* Configure phy */ ret = sh_eth_phy_config(eth); if (ret) { printf(SHETHER_NAME ": phy config timeout\n"); goto err_phy_cfg; } phy = port_info->phydev; ret = phy_startup(phy); if (ret) { printf(SHETHER_NAME ": phy startup failure\n"); return ret; } val = 0; /* Set the transfer speed */ if (phy->speed == 100) { printf(SHETHER_NAME ": 100Base/"); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) sh_eth_write(eth, 1, RTRATE); #elif defined(CONFIG_CPU_SH7724) val = ECMR_RTM; #endif } else if (phy->speed == 10) { printf(SHETHER_NAME ": 10Base/"); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, GECMR_10B, GECMR); #elif defined(CONFIG_CPU_SH7757) sh_eth_write(eth, 0, RTRATE); #endif } #if defined(SH_ETH_TYPE_GETHER) else if (phy->speed == 1000) { printf(SHETHER_NAME ": 1000Base/"); sh_eth_write(eth, GECMR_1000B, GECMR); } #endif /* Check if full duplex mode is supported by the phy */ if (phy->duplex) { printf("Full\n"); sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR); } else { printf("Half\n"); sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); } return ret; err_phy_cfg: return ret; }
static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) { int port = eth->port, ret = 0; u32 val, phy_status; struct sh_eth_info *port_info = ð->port_info[port]; struct eth_device *dev = port_info->dev; /* Configure e-dmac registers */ outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); outl(0, EESIPR(port)); outl(0, TRSCER(port)); outl(0, TFTR(port)); outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); outl(RMCR_RST, RMCR(port)); outl(0, RPADIR(port)); outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); /* Configure e-mac registers */ outl(0, ECSIPR(port)); /* Set Mac address */ val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | dev->enetaddr[2] << 8 | dev->enetaddr[3]; outl(val, MAHR(port)); val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; outl(val, MALR(port)); outl(RFLR_RFL_MIN, RFLR(port)); outl(0, PIPR(port)); outl(APR_AP, APR(port)); outl(MPR_MP, MPR(port)); outl(TPAUSER_TPAUSE, TPAUSER(port)); /* Configure phy */ ret = sh_eth_phy_config(eth); if (ret) { printf(SHETHER_NAME ": phy config timeout\n"); goto err_phy_cfg; } /* Read phy status to finish configuring the e-mac */ phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); /* Set the transfer speed */ if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { printf(SHETHER_NAME ": 100Base/"); outl(GECMR_100B, GECMR(port)); } else { printf(SHETHER_NAME ": 10Base/"); outl(GECMR_10B, GECMR(port)); } /* Check if full duplex mode is supported by the phy */ if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { printf("Full\n"); outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); } else { printf("Half\n"); outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); } return ret; err_phy_cfg: return ret; }
static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) { int port = eth->port, ret = 0; u32 val; struct sh_eth_info *port_info = ð->port_info[port]; struct eth_device *dev = port_info->dev; struct phy_device *phy; /* Configure e-dmac registers */ outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); outl(0, EESIPR(port)); outl(0, TRSCER(port)); outl(0, TFTR(port)); outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); outl(RMCR_RST, RMCR(port)); #if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) outl(0, RPADIR(port)); #endif outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); /* Configure e-mac registers */ #if defined(CONFIG_CPU_SH7757) outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port)); #else outl(0, ECSIPR(port)); #endif /* Set Mac address */ val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | dev->enetaddr[2] << 8 | dev->enetaddr[3]; outl(val, MAHR(port)); val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; outl(val, MALR(port)); outl(RFLR_RFL_MIN, RFLR(port)); #if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) outl(0, PIPR(port)); #endif #if !defined(CONFIG_CPU_SH7724) outl(APR_AP, APR(port)); outl(MPR_MP, MPR(port)); #endif #if defined(CONFIG_CPU_SH7763) outl(TPAUSER_TPAUSE, TPAUSER(port)); #elif defined(CONFIG_CPU_SH7757) outl(TPAUSER_UNLIMITED, TPAUSER(port)); #endif /* Configure phy */ ret = sh_eth_phy_config(eth); if (ret) { printf(SHETHER_NAME ": phy config timeout\n"); goto err_phy_cfg; } phy = port_info->phydev; phy_startup(phy); val = 0; /* Set the transfer speed */ if (phy->speed == 100) { printf(SHETHER_NAME ": 100Base/"); #ifdef CONFIG_CPU_SH7763 outl(GECMR_100B, GECMR(port)); #elif defined(CONFIG_CPU_SH7757) outl(1, RTRATE(port)); #elif defined(CONFIG_CPU_SH7724) val = ECMR_RTM; #endif } else if (phy->speed == 10) { printf(SHETHER_NAME ": 10Base/"); #ifdef CONFIG_CPU_SH7763 outl(GECMR_10B, GECMR(port)); #elif defined(CONFIG_CPU_SH7757) outl(0, RTRATE(port)); #endif } /* Check if full duplex mode is supported by the phy */ if (phy->duplex) { printf("Full\n"); outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); } else { printf("Half\n"); outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); } return ret; err_phy_cfg: return ret; }