static ssize_t smd_shdiag_read(struct file *filp, char __user *buf,size_t count, loff_t *ppos)
{
sharp_smem_common_type *p_sh_smem_common_type = NULL;
struct smem_comm_shdiag smem_comm_data;
D("%s()\n", __func__);
p_sh_smem_common_type = sh_smem_get_common_address();
if( p_sh_smem_common_type != NULL){
smem_comm_data.BootMode = p_sh_smem_common_type->shdiag_BootMode;
smem_comm_data.FlagData = p_sh_smem_common_type->shdiag_FlagData;
smem_comm_data.FirstBoot = p_sh_smem_common_type->shdiag_FirstBoot;
D("BootMode=0x%x FlagData=0x%lx FirstBoot=0x%x\n",
smem_comm_data.BootMode, smem_comm_data.FlagData, smem_comm_data.FirstBoot );
if( copy_to_user( buf, (void *)&smem_comm_data, sizeof(smem_comm_data) ) ){
printk( "copy_to_user failed\n" );
return -EFAULT;
}
} else {
printk("[SH_DIAG]smd_shdiag_probe: smem_alloc FAILE\n");
}
return count;
}
static int __init imx081_init_module(void)
{
int32_t rc = 0;
sharp_smem_common_type *p_sh_smem_common_type = NULL;
int32_t camOtpData_size = 0;
CDBG("%s:%d\n", __func__, __LINE__);
p_sh_smem_common_type = sh_smem_get_common_address();
if(p_sh_smem_common_type != NULL){
camOtpData_size = sizeof(p_sh_smem_common_type->sh_camOtpData);
CDBG("%s camOtpData_size = %d\n", __func__, camOtpData_size);
imx081_diag_data = kmalloc(camOtpData_size, GFP_KERNEL);
if(imx081_diag_data != NULL){
memcpy(imx081_diag_data, &p_sh_smem_common_type->sh_camOtpData[0], camOtpData_size);
}
}
perf_lock_init(&imx081_perf_lock, PERF_LOCK_960000KHz, "camera_imx081");
rc = platform_driver_probe(&imx081_platform_driver,
imx081_platform_probe);
if (!rc)
return rc;
CDBG("%s:%d rc %d\n", __func__, __LINE__, rc);
return i2c_add_driver(&imx081_i2c_driver);
}
static ssize_t secure_show(struct kobject *kobj, struct attribute *attr, char *buf)
{
char buff[32];
sharp_smem_common_type *p_sharp_smem_common_type;
sphinx_printk("secure_show()\n");
if(current->pid != digest_manager_pid)
{
return 0;
}
memset(buff, 0, 32);
p_sharp_smem_common_type = sh_smem_get_common_address();
if( p_sharp_smem_common_type != NULL )
{
memcpy(buff, p_sharp_smem_common_type->shsecure_PassPhrase, 32);
memset(p_sharp_smem_common_type->shsecure_PassPhrase, 0, 32);
memcpy(buf, buff, 32);
}
sphinx_printk("secure_show() : 32\n");
return 32;
}
static void sh_boot_set_bootmode(unsigned short mode)
{
sharp_smem_common_type *p_sharp_smem_common_type;
p_sharp_smem_common_type = sh_smem_get_common_address();
if (p_sharp_smem_common_type != 0)
p_sharp_smem_common_type->sh_boot_mode = mode;
}
unsigned char sh_boot_get_handset(void)
{
sharp_smem_common_type *p_sharp_smem_common_type;
p_sharp_smem_common_type = sh_smem_get_common_address();
if( p_sharp_smem_common_type != 0 )
{
return p_sharp_smem_common_type->sh_hw_handset;
}else{
return 0;
}
}
unsigned long sh_boot_get_bootmode(void)
{
sharp_smem_common_type *p_sharp_smem_common_type;
p_sharp_smem_common_type = sh_smem_get_common_address();
if( p_sharp_smem_common_type != 0 )
{
return p_sharp_smem_common_type->sh_boot_mode;
}else{
return 0;
}
}
/*=============================================================================
FUNCTION
=============================================================================*/
unsigned short sh_boot_get_hw_revision(void)
{
sharp_smem_common_type *p_sharp_smem_common_type;
p_sharp_smem_common_type = sh_smem_get_common_address();
if( p_sharp_smem_common_type != 0 )
{
return p_sharp_smem_common_type->sh_hw_revision;
}else{
return 0xFF;
}
}
static int hw_revision_get(unsigned int *val)
{
sharp_smem_common_type *sh_smem_common = NULL;
sh_smem_common = (sharp_smem_common_type *)sh_smem_get_common_address();
if (sh_smem_common != NULL) {
*val = (unsigned int)sh_smem_common->sh_hw_revision;
}
else{
return -1;
}
return 0;
}
int32_t imx081_smem_write(struct msm_sensor_ctrl_t *s_ctrl,
void __user *argp)
{
struct sensorb_cfg_data *cdata = (struct sensorb_cfg_data *)argp;
long rc = 0;
sharp_smem_common_type *p_sh_smem_common_type = NULL;
int32_t camOtpData_size = 0;
CDBG("%s start\n", __func__);
CDBG("%s smem_info.addr = 0x%0x\n", __func__, cdata->cfg.smem_info.addr);
CDBG("%s smem_info.length = 0x%0x\n", __func__, cdata->cfg.smem_info.length);
p_sh_smem_common_type = sh_smem_get_common_address();
if(p_sh_smem_common_type == NULL){
pr_err("%s p_sh_smem_common_type == NULL\n",__func__);
return -EFAULT;
}
camOtpData_size = sizeof(p_sh_smem_common_type->sh_camOtpData);
if((cdata->cfg.smem_info.addr + cdata->cfg.smem_info.length) > camOtpData_size){
pr_err("%s length error %d : camOtpData_size = %d\n",__func__, (cdata->cfg.smem_info.addr + cdata->cfg.smem_info.length), camOtpData_size);
return -EFAULT;
}
if(imx081_diag_data == NULL){
pr_err("%s imx081_diag_data == NULL\n",__func__);
return -EFAULT;
}
if (copy_from_user(&imx081_diag_data[cdata->cfg.smem_info.addr],
(void *)cdata->cfg.smem_info.data,
cdata->cfg.smem_info.length)){
pr_err("%s copy_from_user error\n",__func__);
return -EFAULT;
}
return rc;
}
static int __devinit gdsc_probe(struct platform_device *pdev)
{
static atomic_t gdsc_count = ATOMIC_INIT(-1);
struct regulator_init_data *init_data;
struct resource *res;
struct gdsc *sc;
uint32_t regval;
bool retain_mem, retain_periph;
int i, ret;
sc = devm_kzalloc(&pdev->dev, sizeof(struct gdsc), GFP_KERNEL);
if (sc == NULL)
return -ENOMEM;
init_data = of_get_regulator_init_data(&pdev->dev, pdev->dev.of_node);
if (init_data == NULL)
return -ENOMEM;
if (of_get_property(pdev->dev.of_node, "parent-supply", NULL))
init_data->supply_regulator = "parent";
ret = of_property_read_string(pdev->dev.of_node, "regulator-name",
&sc->rdesc.name);
if (ret)
return ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL)
return -EINVAL;
sc->gdscr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (sc->gdscr == NULL)
return -ENOMEM;
sc->clock_count = of_property_count_strings(pdev->dev.of_node,
"qcom,clock-names");
if (sc->clock_count == -EINVAL) {
sc->clock_count = 0;
} else if (IS_ERR_VALUE(sc->clock_count)) {
dev_err(&pdev->dev, "Failed to get clock names\n");
return -EINVAL;
}
sc->clocks = devm_kzalloc(&pdev->dev,
sizeof(struct clk *) * sc->clock_count, GFP_KERNEL);
if (!sc->clocks)
return -ENOMEM;
for (i = 0; i < sc->clock_count; i++) {
const char *clock_name;
of_property_read_string_index(pdev->dev.of_node,
"qcom,clock-names", i,
&clock_name);
sc->clocks[i] = devm_clk_get(&pdev->dev, clock_name);
if (IS_ERR(sc->clocks[i])) {
int rc = PTR_ERR(sc->clocks[i]);
if (rc != -EPROBE_DEFER)
dev_err(&pdev->dev, "Failed to get %s\n",
clock_name);
return rc;
}
}
sc->rdesc.id = atomic_inc_return(&gdsc_count);
sc->rdesc.ops = &gdsc_ops;
sc->rdesc.type = REGULATOR_VOLTAGE;
sc->rdesc.owner = THIS_MODULE;
platform_set_drvdata(pdev, sc);
/*
* Disable HW trigger: collapse/restore occur based on registers writes.
* Disable SW override: Use hardware state-machine for sequencing.
*/
regval = readl_relaxed(sc->gdscr);
regval &= ~(HW_CONTROL_MASK | SW_OVERRIDE_MASK);
/* Configure wait time between states. */
regval &= ~(EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK);
regval |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
writel_relaxed(regval, sc->gdscr);
retain_mem = of_property_read_bool(pdev->dev.of_node,
"qcom,retain-mem");
sc->toggle_mem = !retain_mem;
retain_periph = of_property_read_bool(pdev->dev.of_node,
"qcom,retain-periph");
sc->toggle_periph = !retain_periph;
sc->toggle_logic = !of_property_read_bool(pdev->dev.of_node,
"qcom,skip-logic-collapse");
#if defined(CONFIG_MACH_TBS) && defined(CONFIG_ANDROID_ENGINEERING)
{
static sharp_smem_common_type *smemdata = NULL;
unsigned long hw_revision = sh_boot_get_hw_revision();
unsigned int version = socinfo_get_version();
const char* target_names_collapse[] = {
"gdsc_venus", "gdsc_mdss"
};
const char* target_names_retention[] = {
"gdsc_venus", "gdsc_mdss", "gdsc_oxili_gx"
};
if( smemdata == NULL ) {
smemdata = sh_smem_get_common_address();
}
if( (smemdata != NULL)
&& ((hw_revision == HW_VERSION_PP_1) || (hw_revision == HW_VERSION_PP_2)) ) {
if (smemdata->shdiag_rvcflg != SHDIAG_RVCFLG_ON) {
if ( (SOCINFO_VERSION_MAJOR(version) == 2) && (SOCINFO_VERSION_MINOR(version) == 2) ) {
int i = 0;
for(i=0; i<(sizeof(target_names_retention)/sizeof(target_names_retention[0])); i++) {
if( strcmp(sc->rdesc.name, target_names_retention[i]) == 0 ) {
break;
}
}
if( i != (sizeof(target_names_retention)/sizeof(target_names_retention[0])) ) {
if( retain_mem != true ) {
dev_err(&pdev->dev, "%s is forced to use retain_mem\n", sc->rdesc.name);
retain_mem = true;
sc->toggle_mem = !retain_mem;
}
if( retain_periph != true ) {
dev_err(&pdev->dev, "%s is forced to use retain_periph\n", sc->rdesc.name);
retain_periph = true;
sc->toggle_periph = !retain_periph;
}
}
for(i=0; i<(sizeof(target_names_collapse)/sizeof(target_names_collapse[0])); i++) {
if( strcmp(sc->rdesc.name, target_names_collapse[i]) == 0 ) {
break;
}
}
if( i != (sizeof(target_names_collapse)/sizeof(target_names_collapse[0])) ) {
if( sc->toggle_logic != false ) {
dev_err(&pdev->dev, "%s is forced to use skip_logic_collapse\n", sc->rdesc.name);
sc->toggle_logic = false;
}
}
}
}
}
}
#endif
if (!sc->toggle_logic) {
regval &= ~SW_COLLAPSE_MASK;
writel_relaxed(regval, sc->gdscr);
ret = readl_tight_poll_timeout(sc->gdscr, regval,
regval & PWR_ON_MASK, TIMEOUT_US);
if (ret) {
dev_err(&pdev->dev, "%s enable timed out\n",
sc->rdesc.name);
return ret;
}
}
for (i = 0; i < sc->clock_count; i++) {
if (retain_mem || (regval & PWR_ON_MASK))
clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_MEM);
else
clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_MEM);
if (retain_periph || (regval & PWR_ON_MASK))
clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_PERIPH);
else
clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_PERIPH);
}
sc->rdev = regulator_register(&sc->rdesc, &pdev->dev, init_data, sc,
pdev->dev.of_node);
if (IS_ERR(sc->rdev)) {
dev_err(&pdev->dev, "regulator_register(\"%s\") failed.\n",
sc->rdesc.name);
return PTR_ERR(sc->rdev);
}
return 0;
}
