static void iop_write_latency_effect(void)
{
UINT32 data = iop_latency_data;
switch (iop_latency_reg)
{
case 0x1c:
{
if (data & 0x1)
{
sharc_dma_exec(6);
}
break;
}
case 0x1d:
{
if (data & 0x1)
{
sharc_dma_exec(7);
}
break;
}
default: fatalerror("SHARC: iop_write_latency_effect: unknown IOP register %02X", iop_latency_reg);
}
}
static void iop_latency_op(void)
{
UINT32 data = iop_latency_data;
switch (iop_latency_reg)
{
case 0x1c:
{
sharc.dma[6].control = data;
if (data & 0x1) {
sharc_dma_exec(6);
}
break;
}
case 0x1d:
{
sharc.dma[7].control = data;
if (data & 0x1) {
sharc_dma_exec(7);
}
break;
}
default: fatalerror("SHARC: add_iop_latency_op: unknown IOP register %02X", iop_latency_reg);
}
}
static void sharc_reset(void)
{
memset(sharc.internal_ram, 0, 2 * 0x10000 * sizeof(UINT16));
switch(sharc.boot_mode)
{
case BOOT_MODE_EPROM:
{
sharc.dma[6].int_index = 0x20000;
sharc.dma[6].int_modifier = 1;
sharc.dma[6].int_count = 0x100;
sharc.dma[6].ext_index = 0x400000;
sharc.dma[6].ext_modifier = 1;
sharc.dma[6].ext_count = 0x600;
sharc.dma[6].control = 0x2a1;
sharc_dma_exec(6);
dma_op(dmaop_src, dmaop_dst, dmaop_src_modifier, dmaop_dst_modifier,
dmaop_src_count, dmaop_dst_count, dmaop_pmode);
dmaop_cycles = 0;
break;
}
case BOOT_MODE_HOST:
break;
default:
fatalerror("SHARC: Unimplemented boot mode %d", sharc.boot_mode);
}
sharc.pc = 0x20004;
sharc.daddr = sharc.pc + 1;
sharc.faddr = sharc.daddr + 1;
sharc.nfaddr = sharc.faddr+1;
sharc.idle = 0;
sharc.stky = 0x5400000;
interrupt_active = 0;
}
