void bhvm::execute_program (void)
{
try{
while (program_counter < int(program.size()))
{
//std::cout << program[program_counter] << std::endl; // debug... traza todo
exec_instruction(program[program_counter]);
++program_counter;
}
signal_debug(Alarm(MTK_HERE, "bhvm", MTK_SS("end of program." << std::endl << get_status()), alPriorDebug));
} catch(const mtk::Alarm& error) {
Alarm al(MTK_HERE, "bhvm", get_status(), alPriorCritic);
al.Add(error);
signal_error(al);
} catch (std::exception& e) {
signal_error(Alarm(MTK_HERE, "bhvm", MTK_SS("c++ exception " << e.what() << get_status()), alPriorCritic));
} catch(...) {
signal_error(Alarm(MTK_HERE, "bhvm", MTK_SS("unknown error " << get_status()), alPriorCritic));
}
}
int main() {
//////////////////////////////////////////////////////
// init
int16_t* raw_fft_input = (int16_t*) RAW_INPUT_ADDR; // size: 512 * 16 / 32 = 200 (0x100)
int16_t* fft_input = (int16_t*) INPUT_ADDR; // size: 512 * 16 * 2 / 32 * 1.5 = 768 (0x300)
int16_t* fft_output = (int16_t*) OUTPUT_ADDR; // size: 257 * 16 * 2 / 32 * 1.5 = 386 (0x182)
int16_t* window_parameter = (int16_t*) WINDOW_PARA_ADDR; // size: 400 * 16 / 32 = 200 (0xC8).
int16_t* dft_parameter_r = (int16_t*) DFT_PARA_ADDR; // size: 2 * 2 * 16 / 32 = 2 (0x2). 14 fractional bits
int16_t* dft_parameter_i = (int16_t*) DFT_PARA_ADDR + DFT_SIZE * DFT_SIZE * sizeof(int16_t);
int16_t* mfcc_input = (int16_t*) MFCC_INPUT_ADDR; // size: 257 * 16 * 2 / 32 = 257 (0x101)
// int16_t* dct_parameter = DCT_PARA_ADDR;
init_input(raw_fft_input, WINDOW_SIZE);
window_init(window_parameter, WINDOW_SIZE);
dft_init(dft_parameter_r, dft_parameter_i, DFT_SIZE);
// dct_init(dct_parameter);
//////////////////////////////////////////////////////
// PE init
uint16_t inst_no;
set_dnn_insts();
set_nli_parameters();
*REG_WAIT_BEFORE_VDD = 0xff;
*DNN_SRAM_RSTN_0 = 0x000007ff;
*DNN_SRAM_RSTN_1 = 0x000007ff;
*DNN_SRAM_RSTN_2 = 0x000007ff;
*DNN_SRAM_RSTN_3 = 0x000007ff;
delay(3);
*DNN_SRAM_ISOL_0 = 0x000007ff;
*DNN_SRAM_ISOL_1 = 0x000007ff;
*DNN_SRAM_ISOL_2 = 0x000007ff;
*DNN_SRAM_ISOL_3 = 0x000007ff;
delay(3);
*DNN_PG_0 = 0x000007ff;
*DNN_PG_1 = 0x000007ff;
*DNN_PG_2 = 0x000007ff;
*DNN_PG_3 = 0x000007ff;
delay(5);
//*DNN_PG_0 = 0x003ff800;
//*DNN_PG_1 = 0x003ff800;
//*DNN_PG_2 = 0x003ff800;
//*DNN_PG_3 = 0x003ff800;
//delay(3);
*DNN_SRAM_RSTN_0 = 0x000007ff;
*DNN_SRAM_RSTN_0 = 0xffffffff;
*DNN_SRAM_RSTN_1 = 0xffffffff;
*DNN_SRAM_RSTN_2 = 0xffffffff;
*DNN_SRAM_RSTN_3 = 0xffffffff;
delay(3);
// *DNN_RAND_0 = 1;
// *DNN_RAND_1 = 1;
// *DNN_RAND_2 = 1;
// *DNN_RAND_3 = 1;
// delay(3);
//*DNN_SRAM_ISOL_0 = 0x00000000;
//*DNN_SRAM_ISOL_1 = 0x00000000;
//*DNN_SRAM_ISOL_2 = 0x00000000;
//*DNN_SRAM_ISOL_3 = 0x00000000;
//delay(3);
signal_debug(1); // init ends; start counting runtime
//////////////////////////////////////////////////////
// M0 working sequence
// TODO: optimize these arrays
int16_t input_r_dft[FFT_SIZE];
int16_t input_i_dft[FFT_SIZE];
// prepare fft
fft_apply_window(WINDOW_SIZE, raw_fft_input, window_parameter);
prepare_dft_for_fft(WINDOW_SIZE, FFT_SIZE, raw_fft_input, input_r_dft, FFT_NUM, FFT_NUM_BITS, DFT_SIZE);
// dft
dft(DFT_SIZE, FFT_SIZE, input_r_dft, input_i_dft, dft_parameter_r, dft_parameter_i);
prepare_PE_fft_input(fft_input, input_r_dft, input_i_dft, DFT_SIZE, FFT_SIZE, FFT_PREC);
signal_debug(2); // M0 ends; write to PE
// write to PE
uint16_t fft_input_space = FFT_SIZE / 2; // DLC memory occupied. for 16 bits only
write_dnn_sram_16(FFT_START, fft_input, fft_input_space);
signal_debug(0); // start PE runtime, check if memory correct
//////////////////////////////////////////////////////
// PE working sequence
inst_no = 0;
reset_PE(0);
write_instruction(inst_no, 0, 0); // write FFT 0
while (inst_no < FFT_INST - 1) {
if (inst_no % 2 == 0) {
switch_inst_buffer(0, 0);
reset_PE(0);
start_pe_inst(0b0001); // start FFT 0, 2, 4, 6
inst_no++;
write_instruction(inst_no, 0, 1); // write FFT 1, 3, 5, 7
// clock_gate();
} else {
switch_inst_buffer(0, 1);
reset_PE(0);
start_pe_inst(0b0001); // start FFT 1, 3, 5
inst_no++;
write_instruction(inst_no, 0, 0); // write FFT 2, 4, 6
// clock_gate();
}
}
switch_inst_buffer(0, 1);
reset_PE(0);
start_pe_inst(0b0001); // start FFT 7
inst_no++;
// clock_gate();
// finish
wait_until_pe_finish(0b1111);
//////////////////////////////////////////////////////
uint16_t fft_output_space = MFCC_SIZE / 2; // DLC memory occupied. for 16 bits only
read_dnn_sram_16(FFT_START, fft_output, fft_output_space);
extract_fft_output(fft_output, mfcc_input, MFCC_SIZE, FFT_PREC);
// MFCC
// run_mfcc(); // TODO: on PE
// mfcc_to_dnn(test, test1);
signal_done();
delay(7000);
return 1;
// done
}