t_stat clk_reset (DEVICE *dptr) { tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */ sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */ tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ return SCPE_OK; }
t_stat tti_reset (DEVICE *dptr) { tti_buf = 0; tti_csr = 0; tti_int = 0; sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll)); return SCPE_OK; }
int32 ttix (int32 inst, int32 AC) { int32 pulse = inst & 07; /* IOT pulse */ int32 ln = TTX_GETLN (inst); /* line # */ int32 itti = (INT_TTI1 << ln); /* rx intr */ int32 itto = (INT_TTO1 << ln); /* tx intr */ switch (pulse) { /* case IR<9:11> */ case 0: /* KCF */ dev_done = dev_done & ~itti; /* clear flag */ int_req = int_req & ~itti; break; case 1: /* KSF */ return (dev_done & itti)? IOT_SKP + AC: AC; case 2: /* KCC */ dev_done = dev_done & ~itti; /* clear flag */ int_req = int_req & ~itti; sim_activate_abs (&ttix_unit, ttix_unit.wait); /* check soon for more input */ return 0; /* clear AC */ case 4: /* KRS */ return (AC | ttix_buf[ln]); /* return buf */ case 5: /* KIE */ if (AC & 1) int_enable = int_enable | (itti + itto); else int_enable = int_enable & ~(itti + itto); int_req = INT_UPDATE; /* update intr */ break; case 6: /* KRB */ dev_done = dev_done & ~itti; /* clear flag */ int_req = int_req & ~itti; sim_activate_abs (&ttix_unit, ttix_unit.wait); /* check soon for more input */ return ttix_buf[ln]; /* return buf */ default: return (stop_inst << IOT_V_REASON) + AC; } /* end switch */ return AC; }
t_stat tti_reset (DEVICE *dptr) { tti_unit.buf = 0; dev_done = dev_done & ~INT_TTI; /* clear done, int */ int_req = int_req & ~INT_TTI; int_enable = int_enable | INT_TTI; /* set enable */ sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmxr_poll)); return SCPE_OK; }
t_stat tti_reset (DEVICE *dptr) { tmxr_set_console_units (&tti_unit, &tto_unit); tti_unit.buf = 0; tti_csr = 0; CLR_INT (TTI); sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll)); return SCPE_OK; }
t_stat clk_reset (DEVICE *dptr) { if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit); /* disabled? */ else { tmxr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); sim_activate_abs (&clk_unit, tmxr_poll); /* activate unit */ } clk_cntr = 0; /* clear counter */ return SCPE_OK; }
t_stat clk_reset (DEVICE *dptr) { if (CPUT (HAS_LTCR)) clk_fie = clk_fnxm = 0; /* reg there? */ else clk_fie = clk_fnxm = 1; /* no, BEVENT */ clk_tps = clk_default; /* set default tps */ clk_csr = CSR_DONE; /* set done */ CLR_INT (CLK); sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init line clock */ sim_activate_abs (&clk_unit, clk_unit.wait); /* activate unit */ tmr_poll = clk_unit.wait; /* set timer poll */ tmxr_poll = clk_unit.wait; /* set mux poll */ return SCPE_OK; }
t_stat clk_reset (DEVICE *dptr) { int32 t; sim_register_clock_unit (&clk_unit); /* declare clock unit */ clk_csr = 0; CLR_INT (CLK); t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */ sim_activate_abs (&clk_unit, t); /* activate unit */ tmr_poll = t; /* set tmr poll */ tmxr_poll = t * TMXR_MULT; /* set mux poll */ return SCPE_OK; }
t_stat clk_reset (DEVICE *dptr) { sim_register_clock_unit (&clk_unit); /* declare clock unit */ tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */ sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */ tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */ if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */ clk_unit.filebuf = calloc(sizeof(TOY), 1); if (clk_unit.filebuf == NULL) return SCPE_MEM; todr_resync (); } return SCPE_OK; }
t_stat ttp_reset (DEVICE *dptr) { if (dptr->flags & DEV_DIS) sim_cancel (&ttp_unit[TTI]); else sim_activate_abs (&ttp_unit[TTI], KBD_WAIT (ttp_unit[TTI].wait, lfc_poll)); sim_cancel (&ttp_unit[TTO]); CLR_INT (v_TTP); /* clear int */ CLR_ENB (v_TTP); CLR_INT (v_TTP + 1); /* disable int */ CLR_ENB (v_TTP + 1); ttp_karm = ttp_tarm = 0; /* disarm int */ ttp_cmd = 0; ttp_sta = 0; ttp_kchp = 0; return SCPE_OK; }
t_stat tti_rd (int32 *data, int32 PA, int32 access) { switch ((PA >> 1) & 01) { /* decode PA<1> */ case 00: /* tti csr */ *data = tti_csr & TTICSR_IMP; return SCPE_OK; case 01: /* tti buf */ tti_csr = tti_csr & ~CSR_DONE; CLR_INT (TTI); *data = tti_unit.buf & 0377; sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return SCPE_OK; } /* end switch PA */ return SCPE_NXM; }
t_stat clk_reset (DEVICE *dptr) { int32 t; clk_csr = 0; CLR_INT (CLK); t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */ sim_activate_abs (&clk_unit, t); /* activate unit */ tmr_poll = t; /* set tmr poll */ tmxr_poll = t * TMXR_MULT; /* set mux poll */ if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */ clk_unit.filebuf = calloc(sizeof(TOY), 1); if (clk_unit.filebuf == NULL) return SCPE_MEM; todr_resync (); } return SCPE_OK; }
t_stat rtc_reset (DEVICE *dptr) { uint32 i; sim_rtcn_init (rtc_unit.wait, TMR_RTC); /* init base clock */ sim_activate_abs (&rtc_unit, rtc_unit.wait); /* activate unit */ for (i = 0; i < RTC_NUM_EVNTS; i++) { /* clear counters */ if (i < RTC_NUM_CNTRS) { rtc_cntr[i] = 0; rtc_xtra[i] = 0; rtc_indx[i] = 0; rtc_usrv[i] = NULL; if (rtc_register (i, rtc_tps[i], &rtc_cntr_unit[i]) != SCPE_OK) return SCPE_IERR; } else if ((rtc_usrv[i] != NULL) && (rtc_register (i, rtc_indx[i], rtc_usrv[i]) != SCPE_OK)) return SCPE_IERR; } return SCPE_OK; }
int32 tti (int32 IR, int32 AC) { switch (IR & 07) { /* decode IR<9:11> */ case 0: /* KCF */ dev_done = dev_done & ~INT_TTI; /* clear flag */ int_req = int_req & ~INT_TTI; return AC; case 1: /* KSF */ return (dev_done & INT_TTI)? IOT_SKP + AC: AC; case 2: /* KCC */ dev_done = dev_done & ~INT_TTI; /* clear flag */ int_req = int_req & ~INT_TTI; return 0; /* clear AC */ case 4: /* KRS */ return (AC | tti_unit.buf); /* return buffer */ case 5: /* KIE */ if (AC & 1) int_enable = int_enable | (INT_TTI+INT_TTO); else int_enable = int_enable & ~(INT_TTI+INT_TTO); int_req = INT_UPDATE; /* update interrupts */ return AC; case 6: /* KRB */ dev_done = dev_done & ~INT_TTI; /* clear flag */ int_req = int_req & ~INT_TTI; sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return (tti_unit.buf); /* return buffer */ default: return (stop_inst << IOT_V_REASON) + AC; } /* end switch */ }
static void resync_clock (void) { coschedulable = (ticks [rate] == 1000 /* the clock can be coscheduled if the rate */ && limit_register == 100); /* is 1 msec and the limit is 100 ticks */ if (clk_unit [0].flags & UNIT_CALTIME /* if the clock is in calibrated timing mode */ && coschedulable /* and may be coscheduled with the process clock */ && cpu_is_calibrated) { /* and the process clock is calibrated */ clk_unit [0].wait = sim_activate_time (cpu_pclk_uptr); /* then synchronize with it */ coscheduled = TRUE; /* the clock is coscheduled with the process clock */ } else { /* otherwise */ clk_unit [0].wait = delay [rate]; /* set up an independent clock */ coscheduled = FALSE; /* the clock is not coscheduled with the process clock */ } dprintf (clk_dev, DEB_PSERV, "Rate %s delay %d service rescheduled\n", rate_name [rate], clk_unit [0].wait); sim_activate_abs (&clk_unit [0], clk_unit [0].wait); /* restart the clock */ return; }