struct pipe_screen * virgl_create_screen(struct virgl_winsys *vws) { struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen); if (!screen) return NULL; screen->vws = vws; screen->base.get_name = virgl_get_name; screen->base.get_vendor = virgl_get_vendor; screen->base.get_param = virgl_get_param; screen->base.get_shader_param = virgl_get_shader_param; screen->base.get_paramf = virgl_get_paramf; screen->base.is_format_supported = virgl_is_format_supported; screen->base.destroy = virgl_destroy_screen; screen->base.context_create = virgl_context_create; screen->base.flush_frontbuffer = virgl_flush_frontbuffer; screen->base.get_timestamp = virgl_get_timestamp; screen->base.fence_reference = virgl_fence_reference; //screen->base.fence_signalled = virgl_fence_signalled; screen->base.fence_finish = virgl_fence_finish; virgl_init_screen_resource_functions(&screen->base); vws->get_caps(vws, &screen->caps); screen->refcnt = 1; slab_create_parent(&screen->texture_transfer_pool, sizeof(struct virgl_transfer), 16); util_format_s3tc_init(); return &screen->base; }
struct pipe_screen* r300_screen_create(struct radeon_winsys *rws) { struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen); if (!r300screen) { FREE(r300screen); return NULL; } rws->query_info(rws, &r300screen->info); r300_init_debug(r300screen); r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps); if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK)) r300screen->caps.zmask_ram = 0; if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ)) r300screen->caps.hiz_ram = 0; r300screen->rws = rws; r300screen->screen.destroy = r300_destroy_screen; r300screen->screen.get_name = r300_get_name; r300screen->screen.get_vendor = r300_get_vendor; r300screen->screen.get_device_vendor = r300_get_device_vendor; r300screen->screen.get_param = r300_get_param; r300screen->screen.get_shader_param = r300_get_shader_param; r300screen->screen.get_paramf = r300_get_paramf; r300screen->screen.get_video_param = r300_get_video_param; r300screen->screen.is_format_supported = r300_is_format_supported; r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; r300screen->screen.context_create = r300_create_context; r300screen->screen.fence_reference = r300_fence_reference; r300screen->screen.fence_finish = r300_fence_finish; r300_init_screen_resource_functions(r300screen); slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64); util_format_s3tc_init(); pipe_mutex_init(r300screen->cmask_mutex); return &r300screen->screen; }
struct pipe_screen * etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, struct renderonly *ro) { struct etna_screen *screen = CALLOC_STRUCT(etna_screen); struct pipe_screen *pscreen; uint64_t val; if (!screen) return NULL; pscreen = &screen->base; screen->dev = dev; screen->gpu = gpu; screen->ro = renderonly_dup(ro); if (!screen->ro) { DBG("could not create renderonly object"); goto fail; } etna_mesa_debug = debug_get_option_etna_mesa_debug(); /* FIXME: Disable tile status for stability at the moment */ etna_mesa_debug |= ETNA_DBG_NO_TS; screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); if (!screen->pipe) { DBG("could not create 3d pipe"); goto fail; } if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) { DBG("could not get ETNA_GPU_MODEL"); goto fail; } screen->model = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) { DBG("could not get ETNA_GPU_REVISION"); goto fail; } screen->revision = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) { DBG("could not get ETNA_GPU_FEATURES_0"); goto fail; } screen->features[0] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) { DBG("could not get ETNA_GPU_FEATURES_1"); goto fail; } screen->features[1] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) { DBG("could not get ETNA_GPU_FEATURES_2"); goto fail; } screen->features[2] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) { DBG("could not get ETNA_GPU_FEATURES_3"); goto fail; } screen->features[3] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) { DBG("could not get ETNA_GPU_FEATURES_4"); goto fail; } screen->features[4] = val; if (!etna_get_specs(screen)) goto fail; pscreen->destroy = etna_screen_destroy; pscreen->get_param = etna_screen_get_param; pscreen->get_paramf = etna_screen_get_paramf; pscreen->get_shader_param = etna_screen_get_shader_param; pscreen->get_name = etna_screen_get_name; pscreen->get_vendor = etna_screen_get_vendor; pscreen->get_device_vendor = etna_screen_get_device_vendor; pscreen->get_timestamp = etna_screen_get_timestamp; pscreen->context_create = etna_context_create; pscreen->is_format_supported = etna_screen_is_format_supported; etna_fence_screen_init(pscreen); etna_query_screen_init(pscreen); etna_resource_screen_init(pscreen); slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16); return pscreen; fail: etna_screen_destroy(pscreen); return NULL; }
struct pipe_screen * fd_screen_create(struct fd_device *dev) { struct fd_screen *screen = CALLOC_STRUCT(fd_screen); struct pipe_screen *pscreen; uint64_t val; fd_mesa_debug = debug_get_option_fd_mesa_debug(); if (fd_mesa_debug & FD_DBG_NOBIN) fd_binning_enabled = false; glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120); if (!screen) return NULL; pscreen = &screen->base; screen->dev = dev; screen->refcnt = 1; // maybe this should be in context? screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D); if (!screen->pipe) { DBG("could not create 3d pipe"); goto fail; } if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) { DBG("could not get GMEM size"); goto fail; } screen->gmemsize_bytes = val; if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) { DBG("could not get device-id"); goto fail; } screen->device_id = val; if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) { DBG("could not get gpu freq"); /* this limits what performance related queries are * supported but is not fatal */ screen->max_freq = 0; } else { screen->max_freq = val; if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0) screen->has_timestamp = true; } if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) { DBG("could not get gpu-id"); goto fail; } screen->gpu_id = val; if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) { DBG("could not get chip-id"); /* older kernels may not have this property: */ unsigned core = screen->gpu_id / 100; unsigned major = (screen->gpu_id % 100) / 10; unsigned minor = screen->gpu_id % 10; unsigned patch = 0; /* assume the worst */ val = (patch & 0xff) | ((minor & 0xff) << 8) | ((major & 0xff) << 16) | ((core & 0xff) << 24); } screen->chip_id = val; if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) { DBG("could not get # of rings"); screen->priority_mask = 0; } else { /* # of rings equates to number of unique priority values: */ screen->priority_mask = (1 << val) - 1; } struct sysinfo si; sysinfo(&si); screen->ram_size = si.totalram; DBG("Pipe Info:"); DBG(" GPU-id: %d", screen->gpu_id); DBG(" Chip-id: 0x%08x", screen->chip_id); DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes); /* explicitly checking for GPU revisions that are known to work. This * may be overly conservative for a3xx, where spoofing the gpu_id with * the blob driver seems to generate identical cmdstream dumps. But * on a2xx, there seem to be small differences between the GPU revs * so it is probably better to actually test first on real hardware * before enabling: * * If you have a different adreno version, feel free to add it to one * of the cases below and see what happens. And if it works, please * send a patch ;-) */ switch (screen->gpu_id) { case 220: fd2_screen_init(pscreen); break; case 305: case 307: case 320: case 330: fd3_screen_init(pscreen); break; case 420: case 430: fd4_screen_init(pscreen); break; case 530: fd5_screen_init(pscreen); break; default: debug_printf("unsupported GPU: a%03d\n", screen->gpu_id); goto fail; } if (screen->gpu_id >= 500) { screen->gmem_alignw = 64; screen->gmem_alignh = 32; screen->num_vsc_pipes = 16; } else { screen->gmem_alignw = 32; screen->gmem_alignh = 32; screen->num_vsc_pipes = 8; } /* NOTE: don't enable reordering on a2xx, since completely untested. * Also, don't enable if we have too old of a kernel to support * growable cmdstream buffers, since memory requirement for cmdstream * buffers would be too much otherwise. */ if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)) screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER); fd_bc_init(&screen->batch_cache); (void) mtx_init(&screen->lock, mtx_plain); pscreen->destroy = fd_screen_destroy; pscreen->get_param = fd_screen_get_param; pscreen->get_paramf = fd_screen_get_paramf; pscreen->get_shader_param = fd_screen_get_shader_param; pscreen->get_compute_param = fd_get_compute_param; pscreen->get_compiler_options = fd_get_compiler_options; fd_resource_screen_init(pscreen); fd_query_screen_init(pscreen); pscreen->get_name = fd_screen_get_name; pscreen->get_vendor = fd_screen_get_vendor; pscreen->get_device_vendor = fd_screen_get_device_vendor; pscreen->get_timestamp = fd_screen_get_timestamp; pscreen->fence_reference = fd_fence_ref; pscreen->fence_finish = fd_fence_finish; pscreen->fence_get_fd = fd_fence_get_fd; slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16); return pscreen; fail: fd_screen_destroy(pscreen); return NULL; }
struct pipe_screen * etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, struct renderonly *ro) { struct etna_screen *screen = CALLOC_STRUCT(etna_screen); struct pipe_screen *pscreen; drmVersionPtr version; uint64_t val; if (!screen) return NULL; pscreen = &screen->base; screen->dev = dev; screen->gpu = gpu; screen->ro = renderonly_dup(ro); screen->refcnt = 1; if (!screen->ro) { DBG("could not create renderonly object"); goto fail; } version = drmGetVersion(screen->ro->gpu_fd); screen->drm_version = ETNA_DRM_VERSION(version->version_major, version->version_minor); drmFreeVersion(version); etna_mesa_debug = debug_get_option_etna_mesa_debug(); /* Disable autodisable for correct rendering with TS */ etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE; screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); if (!screen->pipe) { DBG("could not create 3d pipe"); goto fail; } if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) { DBG("could not get ETNA_GPU_MODEL"); goto fail; } screen->model = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) { DBG("could not get ETNA_GPU_REVISION"); goto fail; } screen->revision = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) { DBG("could not get ETNA_GPU_FEATURES_0"); goto fail; } screen->features[0] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) { DBG("could not get ETNA_GPU_FEATURES_1"); goto fail; } screen->features[1] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) { DBG("could not get ETNA_GPU_FEATURES_2"); goto fail; } screen->features[2] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) { DBG("could not get ETNA_GPU_FEATURES_3"); goto fail; } screen->features[3] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) { DBG("could not get ETNA_GPU_FEATURES_4"); goto fail; } screen->features[4] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) { DBG("could not get ETNA_GPU_FEATURES_5"); goto fail; } screen->features[5] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) { DBG("could not get ETNA_GPU_FEATURES_6"); goto fail; } screen->features[6] = val; if (!etna_get_specs(screen)) goto fail; /* apply debug options that disable individual features */ if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z; if (DBG_ENABLED(ETNA_DBG_NO_TS)) screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE)) screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE; if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) screen->specs.can_supertile = 0; if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF)) screen->specs.single_buffer = 0; pscreen->destroy = etna_screen_destroy; pscreen->get_param = etna_screen_get_param; pscreen->get_paramf = etna_screen_get_paramf; pscreen->get_shader_param = etna_screen_get_shader_param; pscreen->get_name = etna_screen_get_name; pscreen->get_vendor = etna_screen_get_vendor; pscreen->get_device_vendor = etna_screen_get_device_vendor; pscreen->get_timestamp = etna_screen_get_timestamp; pscreen->context_create = etna_context_create; pscreen->is_format_supported = etna_screen_is_format_supported; pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers; etna_fence_screen_init(pscreen); etna_query_screen_init(pscreen); etna_resource_screen_init(pscreen); util_dynarray_init(&screen->supported_pm_queries, NULL); slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16); if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON) etna_pm_query_setup(screen); return pscreen; fail: etna_screen_destroy(pscreen); return NULL; }
struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, const struct pipe_screen_config *config) { struct si_screen *sscreen = CALLOC_STRUCT(si_screen); unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i; if (!sscreen) { return NULL; } sscreen->ws = ws; ws->query_info(ws, &sscreen->info); if (sscreen->info.chip_class >= GFX9) { sscreen->se_tile_repeat = 32 * sscreen->info.max_se; } else { ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config, &sscreen->pa_sc_raster_config_1, &sscreen->se_tile_repeat); } sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0); sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", debug_options, 0); /* Set functions first. */ sscreen->b.context_create = si_pipe_create_context; sscreen->b.destroy = si_destroy_screen; sscreen->b.set_max_shader_compiler_threads = si_set_max_shader_compiler_threads; sscreen->b.is_parallel_shader_compilation_finished = si_is_parallel_shader_compilation_finished; si_init_screen_get_functions(sscreen); si_init_screen_buffer_functions(sscreen); si_init_screen_fence_functions(sscreen); si_init_screen_state_functions(sscreen); si_init_screen_texture_functions(sscreen); si_init_screen_query_functions(sscreen); /* Set these flags in debug_flags early, so that the shader cache takes * them into account. */ if (driQueryOptionb(config->options, "glsl_correct_derivatives_after_discard")) sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL); if (driQueryOptionb(config->options, "radeonsi_enable_sisched")) sscreen->debug_flags |= DBG(SI_SCHED); if (sscreen->debug_flags & DBG(INFO)) ac_print_gpu_info(&sscreen->info); slab_create_parent(&sscreen->pool_transfers, sizeof(struct si_transfer), 64); sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1)); if (sscreen->force_aniso >= 0) { printf("radeonsi: Forcing anisotropy filter to %ix\n", /* round down to a power of two */ 1 << util_logbase2(sscreen->force_aniso)); } (void) mtx_init(&sscreen->aux_context_lock, mtx_plain); (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain); si_init_gs_info(sscreen); if (!si_init_shader_cache(sscreen)) { FREE(sscreen); return NULL; } si_disk_cache_create(sscreen); /* Determine the number of shader compiler threads. */ hw_threads = sysconf(_SC_NPROCESSORS_ONLN); if (hw_threads >= 12) { num_comp_hi_threads = hw_threads * 3 / 4; num_comp_lo_threads = hw_threads / 3; } else if (hw_threads >= 6) { num_comp_hi_threads = hw_threads - 2; num_comp_lo_threads = hw_threads / 2; } else if (hw_threads >= 2) { num_comp_hi_threads = hw_threads - 1; num_comp_lo_threads = hw_threads / 2; } else { num_comp_hi_threads = 1; num_comp_lo_threads = 1; } num_comp_hi_threads = MIN2(num_comp_hi_threads, ARRAY_SIZE(sscreen->compiler)); num_comp_lo_threads = MIN2(num_comp_lo_threads, ARRAY_SIZE(sscreen->compiler_lowp)); if (!util_queue_init(&sscreen->shader_compiler_queue, "sh", 64, num_comp_hi_threads, UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) { si_destroy_shader_cache(sscreen); FREE(sscreen); return NULL; } if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority, "shlo", 64, num_comp_lo_threads, UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY | UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) { si_destroy_shader_cache(sscreen); FREE(sscreen); return NULL; } if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false)) si_init_perfcounters(sscreen); /* Determine tessellation ring info. */ bool double_offchip_buffers = sscreen->info.chip_class >= CIK && sscreen->info.family != CHIP_CARRIZO && sscreen->info.family != CHIP_STONEY; /* This must be one less than the maximum number due to a hw limitation. * Various hardware bugs in SI, CIK, and GFX9 need this. */ unsigned max_offchip_buffers_per_se; /* Only certain chips can use the maximum value. */ if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20) max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64; else max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63; unsigned max_offchip_buffers = max_offchip_buffers_per_se * sscreen->info.max_se; unsigned offchip_granularity; /* Hawaii has a bug with offchip buffers > 256 that can be worked * around by setting 4K granularity. */ if (sscreen->info.family == CHIP_HAWAII) { sscreen->tess_offchip_block_dw_size = 4096; offchip_granularity = V_03093C_X_4K_DWORDS; } else { sscreen->tess_offchip_block_dw_size = 8192; offchip_granularity = V_03093C_X_8K_DWORDS; } sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se; assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0); sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4; if (sscreen->info.chip_class >= CIK) { if (sscreen->info.chip_class >= VI) --max_offchip_buffers; sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) | S_03093C_OFFCHIP_GRANULARITY(offchip_granularity); } else { assert(offchip_granularity == V_03093C_X_8K_DWORDS); sscreen->vgt_hs_offchip_param = S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); } /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc. * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/ sscreen->has_clear_state = sscreen->info.chip_class >= CIK && sscreen->info.drm_major == 3; sscreen->has_distributed_tess = sscreen->info.chip_class >= VI && sscreen->info.max_se >= 2; sscreen->has_draw_indirect_multi = (sscreen->info.family >= CHIP_POLARIS10) || (sscreen->info.chip_class == VI && sscreen->info.pfp_fw_version >= 121 && sscreen->info.me_fw_version >= 87) || (sscreen->info.chip_class == CIK && sscreen->info.pfp_fw_version >= 211 && sscreen->info.me_fw_version >= 173) || (sscreen->info.chip_class == SI && sscreen->info.pfp_fw_version >= 79 && sscreen->info.me_fw_version >= 142); sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI && sscreen->info.max_se >= 2 && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER)); sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights"); sscreen->commutative_blend_add = driQueryOptionb(config->options, "radeonsi_commutative_blend_add"); { #define OPT_BOOL(name, dflt, description) \ sscreen->options.name = \ driQueryOptionb(config->options, "radeonsi_"#name); #include "si_debug_options.h" } sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 || sscreen->info.family == CHIP_RAVEN; sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 && sscreen->info.family <= CHIP_POLARIS12) || sscreen->info.family == CHIP_VEGA10 || sscreen->info.family == CHIP_RAVEN; sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 || sscreen->info.family == CHIP_RAVEN; sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2; /* Only enable primitive binning on APUs by default. */ sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN || sscreen->info.family == CHIP_RAVEN2; sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN || sscreen->info.family == CHIP_RAVEN2; /* Process DPBB enable flags. */ if (sscreen->debug_flags & DBG(DPBB)) { sscreen->dpbb_allowed = true; if (sscreen->debug_flags & DBG(DFSM)) sscreen->dfsm_allowed = true; } /* Process DPBB disable flags. */ if (sscreen->debug_flags & DBG(NO_DPBB)) { sscreen->dpbb_allowed = false; sscreen->dfsm_allowed = false; } else if (sscreen->debug_flags & DBG(NO_DFSM)) { sscreen->dfsm_allowed = false; } /* While it would be nice not to have this flag, we are constrained * by the reality that LLVM 5.0 doesn't have working VGPR indexing * on GFX9. */ sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI; /* Some chips have RB+ registers, but don't support RB+. Those must * always disable it. */ if (sscreen->info.family == CHIP_STONEY || sscreen->info.chip_class >= GFX9) { sscreen->has_rbplus = true; sscreen->rbplus_allowed = !(sscreen->debug_flags & DBG(NO_RB_PLUS)) && (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_RAVEN || sscreen->info.family == CHIP_RAVEN2); } sscreen->dcc_msaa_allowed = !(sscreen->debug_flags & DBG(NO_DCC_MSAA)); sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI; (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain); sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0; sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 | SI_CONTEXT_INV_VMEM_L1; if (sscreen->info.chip_class <= VI) { sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2; sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; } if (debug_get_bool_option("RADEON_DUMP_SHADERS", false)) sscreen->debug_flags |= DBG_ALL_SHADERS; /* Syntax: * EQAA=s,z,c * Example: * EQAA=8,4,2 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples. * Constraints: * s >= z >= c (ignoring this only wastes memory) * s = [2..16] * z = [2..8] * c = [2..8] * * Only MSAA color and depth buffers are overriden. */ if (sscreen->info.has_eqaa_surface_allocator) { const char *eqaa = debug_get_option("EQAA", NULL); unsigned s,z,f; if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) { sscreen->eqaa_force_coverage_samples = s; sscreen->eqaa_force_z_samples = z; sscreen->eqaa_force_color_samples = f; } } for (i = 0; i < num_comp_hi_threads; i++) si_init_compiler(sscreen, &sscreen->compiler[i]); for (i = 0; i < num_comp_lo_threads; i++) si_init_compiler(sscreen, &sscreen->compiler_lowp[i]); /* Create the auxiliary context. This must be done last. */ sscreen->aux_context = si_create_context( &sscreen->b, sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0); if (sscreen->options.aux_debug) { struct u_log_context *log = CALLOC_STRUCT(u_log_context); u_log_context_init(log); sscreen->aux_context->set_log_context(sscreen->aux_context, log); } if (sscreen->debug_flags & DBG(TEST_DMA)) si_test_dma(sscreen); if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) { si_test_dma_perf(sscreen); } if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) | DBG(TEST_VMFAULT_SDMA) | DBG(TEST_VMFAULT_SHADER))) si_test_vmfault(sscreen); if (sscreen->debug_flags & DBG(TEST_GDS)) si_test_gds((struct si_context*)sscreen->aux_context); if (sscreen->debug_flags & DBG(TEST_GDS_MM)) { si_test_gds_memory_management((struct si_context*)sscreen->aux_context, 32 * 1024, 4, RADEON_DOMAIN_GDS); } if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) { si_test_gds_memory_management((struct si_context*)sscreen->aux_context, 4, 1, RADEON_DOMAIN_OA); } return &sscreen->b; }