/*
* Setup SMC for the given ATA timing.
*/
static int pata_at32_setup_timing(struct device *dev,
struct at32_ide_info *info,
const struct ata_timing *ata)
{
struct smc_config *smc = &info->smc;
struct smc_timing timing;
int active;
int recover;
memset(&timing, 0, sizeof(struct smc_timing));
/* Total cycle time */
timing.read_cycle = ata->cyc8b;
/* DIOR <= CFIOR timings */
timing.nrd_setup = ata->setup;
timing.nrd_pulse = ata->act8b;
timing.nrd_recover = ata->rec8b;
/* Convert nanosecond timing to clock cycles */
smc_set_timing(smc, &timing);
/* Add one extra cycle setup due to signal ring */
smc->nrd_setup = smc->nrd_setup + 1;
active = smc->nrd_setup + smc->nrd_pulse;
recover = smc->read_cycle - active;
/* Need at least two cycles recovery */
if (recover < 2)
smc->read_cycle = active + 2;
/* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
smc->ncs_read_setup = 1;
smc->ncs_read_pulse = smc->read_cycle - 2;
/* Write timings same as read timings */
smc->write_cycle = smc->read_cycle;
smc->nwe_setup = smc->nrd_setup;
smc->nwe_pulse = smc->nrd_pulse;
smc->ncs_write_setup = smc->ncs_read_setup;
smc->ncs_write_pulse = smc->ncs_read_pulse;
/* Do some debugging output of ATA and SMC timings */
dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n",
ata->cyc8b, ata->setup, ata->act8b, ata->rec8b);
dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n",
smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
smc->ncs_read_setup, smc->ncs_read_pulse);
/* Finally, configure the SMC */
return smc_set_configuration(info->cs, smc);
}
static int __init mimc200_flash_init(void)
{
int ret;
smc_set_timing(&flash_config, &flash_timing);
ret = smc_set_configuration(0, &flash_config);
if (ret < 0) {
printk(KERN_ERR "mimc200: failed to set 'System' NOR flash timing\n");
return ret;
}
ret = smc_set_configuration(1, &flash_config);
if (ret < 0) {
printk(KERN_ERR "mimc200: failed to set 'Data' NOR flash timing\n");
return ret;
}
platform_device_register(&flash_device_system);
platform_device_register(&flash_device_data);
return 0;
}
/* This needs to be called after the SMC has been initialized */
static int __init hammerhead_flash_init(void)
{
int ret;
smc_set_timing(&flash_config, &flash_timing);
ret = smc_set_configuration(0, &flash_config);
if (ret < 0) {
printk(KERN_ERR "hammerhead: failed to set NOR flash timing\n");
return ret;
}
platform_device_register(&flash_devi
static int __init hammerhead_usbh_init(void)
{
struct clk *gclk;
struct clk *osc;
int ret;
/* setup smc for usbh */
smc_set_timing(&isp1160_config, &isp1160_timing);
ret = smc_set_configuration(2, &isp1160_config);
if (ret < 0) {
printk(KERN_ERR
"hammerhead: failed to set ISP1160 USBH timing\n");
return ret;
}
/* setup gclk0 to run from osc1 */
gclk = clk_get(NULL, "gclk0");
if (IS_ERR(gclk)) {
ret = PTR_ERR(gclk);
goto err_gclk;
}
osc = clk_get(NULL, "osc1");
if (IS_ERR(osc)) {
ret = PTR_ERR(osc);
goto err_osc;
}
ret = clk_set_parent(gclk, osc);
if (ret < 0) {
pr_debug("hammerhead: failed to set osc1 for USBH clock\n");
goto err_set_clk;
}
/* set clock to 6MHz */
clk_set_rate(gclk, 6000000);
/* and enable */
clk_enable(gclk);
/* select GCLK0 peripheral function */
at32_select_periph(GPIO_PIOA_BASE, HAMMERHEAD_USB_PERIPH_GCLK0,
GPIO_PERIPH_A, 0);
/* enable CS2 peripheral function */
at32_select_periph(GPIO_PIOE_BASE, HAMMERHEAD_USB_PERIPH_CS2,
GPIO_PERIPH_A, 0);
/* H_WAKEUP must be driven low */
at32_select_gpio(GPIO_PIN_PA(8), AT32_GPIOF_OUTPUT);
/* Select EXTINT0 for PB25 */
at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_USB_PERIPH_EXTINT0,
GPIO_PERIPH_A, 0);
/* register usbh device driver */
platform_device_register(&isp1160_device);
err_set_clk:
clk_put(osc);
err_osc:
clk_put(gclk);
err_gclk:
return ret;
}
