static void smm_install(void) { device_t dev = PCI_DEV(0, 0, 0); device_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1); u32 smm_base = 0xa0000; struct ied_header ied = { .signature = "INTEL RSVD", .size = IED_SIZE, .reserved = {0}, }; /* The first CPU running this gets to copy the SMM handler. But not all * of them. */ if (smm_handler_copied) return; smm_handler_copied = 1; /* enable the SMM memory window */ pci_write_config8(qpdev, QPD0F1_SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); #if CONFIG_SMM_TSEG smm_base = pci_read_config32(dev, TSEG) & ~1; #endif /* copy the real SMM handler */ printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base); memcpy((void *)smm_base, &_binary_smm_start, (size_t)(&_binary_smm_end - &_binary_smm_start)); /* copy the IED header into place */ if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) { /* Top of TSEG region */ smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE; printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n", smm_base); memcpy((void *)smm_base, &ied, sizeof(ied)); } wbinvd(); /* close the SMM memory window and enable normal SMM */ pci_write_config8(qpdev, QPD0F1_SMRAM, G_SMRAME | C_BASE_SEG); } void smm_init(void) { #if CONFIG_ELOG /* Log events from chipset before clearing */ pch_log_state(); #endif /* Put SMM code to 0xa0000 */ smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ smm_relocate(); /* We're done. Make sure SMIs can happen! */ smi_set_eos(); }
void smm_init(void) { /* Put SMM code to 0xa0000 */ smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ smm_relocate(); /* We're done. Make sure SMIs can happen! */ smi_set_eos(); }
void smm_init(void) { smm_relocate(); smm_install(); smi_set_eos(); }