int
smsc_miibus_readreg(struct device *dev, int phy, int reg)
{
struct smsc_softc *sc = (struct smsc_softc *)dev;
uint32_t addr;
uint32_t val = 0;
smsc_lock_mii(sc);
if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) {
smsc_warn_printf(sc, "MII is busy\n");
goto done;
}
addr = (phy << 11) | (reg << 6) | SMSC_MII_READ;
smsc_write_reg(sc, SMSC_MII_ADDR, addr);
if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0)
smsc_warn_printf(sc, "MII read timeout\n");
smsc_read_reg(sc, SMSC_MII_DATA, &val);
smsc_unlock_mii(sc);
done:
return (val & 0xFFFF);
}
void
smsc_miibus_writereg(device_t dev, int phy, int reg, int val)
{
struct smsc_softc *sc = device_private(dev);
uint32_t addr;
if (sc->sc_phyno != phy)
return;
smsc_lock_mii(sc);
if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) {
smsc_warn_printf(sc, "MII is busy\n");
smsc_unlock_mii(sc);
return;
}
smsc_write_reg(sc, SMSC_MII_DATA, val);
addr = (phy << 11) | (reg << 6) | SMSC_MII_WRITE;
smsc_write_reg(sc, SMSC_MII_ADDR, addr);
smsc_unlock_mii(sc);
if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0)
smsc_warn_printf(sc, "MII write timeout\n");
}
int
smsc_chip_init(struct smsc_softc *sc)
{
int err;
uint32_t reg_val;
int burst_cap;
/* Enter H/W config mode */
smsc_write_reg(sc, SMSC_HW_CFG, SMSC_HW_CFG_LRST);
if ((err = smsc_wait_for_bits(sc, SMSC_HW_CFG,
SMSC_HW_CFG_LRST)) != 0) {
smsc_warn_printf(sc, "timed-out waiting for reset to "
"complete\n");
goto init_failed;
}
/* Reset the PHY */
smsc_write_reg(sc, SMSC_PM_CTRL, SMSC_PM_CTRL_PHY_RST);
if ((err = smsc_wait_for_bits(sc, SMSC_PM_CTRL,
SMSC_PM_CTRL_PHY_RST) != 0)) {
smsc_warn_printf(sc, "timed-out waiting for phy reset to "
"complete\n");
goto init_failed;
}
usbd_delay_ms(sc->sc_udev, 40);
/* Set the mac address */
if ((err = smsc_setmacaddress(sc, sc->sc_ac.ac_enaddr)) != 0) {
smsc_warn_printf(sc, "failed to set the MAC address\n");
goto init_failed;
}
/*
* Don't know what the HW_CFG_BIR bit is, but following the reset
* sequence as used in the Linux driver.
*/
if ((err = smsc_read_reg(sc, SMSC_HW_CFG, ®_val)) != 0) {
smsc_warn_printf(sc, "failed to read HW_CFG: %d\n", err);
goto init_failed;
}
reg_val |= SMSC_HW_CFG_BIR;
smsc_write_reg(sc, SMSC_HW_CFG, reg_val);
/*
* There is a so called 'turbo mode' that the linux driver supports, it
* seems to allow you to jam multiple frames per Rx transaction.
* By default this driver supports that and therefore allows multiple
* frames per URB.
*
* The xfer buffer size needs to reflect this as well, therefore based
* on the calculations in the Linux driver the RX bufsize is set to
* 18944,
* bufsz = (16 * 1024 + 5 * 512)
*
* Burst capability is the number of URBs that can be in a burst of
* data/ethernet frames.
*/
#ifdef SMSC_TURBO
if (sc->sc_udev->speed == USB_SPEED_HIGH)
burst_cap = 37;
else
burst_cap = 128;
#else
burst_cap = 0;
#endif
smsc_write_reg(sc, SMSC_BURST_CAP, burst_cap);
/* Set the default bulk in delay (magic value from Linux driver) */
smsc_write_reg(sc, SMSC_BULK_IN_DLY, 0x00002000);
/*
* Initialise the RX interface
*/
if ((err = smsc_read_reg(sc, SMSC_HW_CFG, ®_val)) < 0) {
smsc_warn_printf(sc, "failed to read HW_CFG: (err = %d)\n",
err);
goto init_failed;
}
/*
* The following setings are used for 'turbo mode', a.k.a multiple
* frames per Rx transaction (again info taken form Linux driver).
*/
#ifdef SMSC_TURBO
reg_val |= (SMSC_HW_CFG_MEF | SMSC_HW_CFG_BCE);
#endif
smsc_write_reg(sc, SMSC_HW_CFG, reg_val);
/* Clear the status register ? */
smsc_write_reg(sc, SMSC_INTR_STATUS, 0xffffffff);
/* Read and display the revision register */
if ((err = smsc_read_reg(sc, SMSC_ID_REV, &sc->sc_rev_id)) < 0) {
smsc_warn_printf(sc, "failed to read ID_REV (err = %d)\n", err);
goto init_failed;
}
/* GPIO/LED setup */
reg_val = SMSC_LED_GPIO_CFG_SPD_LED | SMSC_LED_GPIO_CFG_LNK_LED |
SMSC_LED_GPIO_CFG_FDX_LED;
smsc_write_reg(sc, SMSC_LED_GPIO_CFG, reg_val);
/*
* Initialise the TX interface
*/
smsc_write_reg(sc, SMSC_FLOW, 0);
smsc_write_reg(sc, SMSC_AFC_CFG, AFC_CFG_DEFAULT);
/* Read the current MAC configuration */
if ((err = smsc_read_reg(sc, SMSC_MAC_CSR, &sc->sc_mac_csr)) < 0) {
smsc_warn_printf(sc, "failed to read MAC_CSR (err=%d)\n", err);
goto init_failed;
}
/* Vlan */
smsc_write_reg(sc, SMSC_VLAN1, (uint32_t)ETHERTYPE_VLAN);
/*
* Start TX
*/
sc->sc_mac_csr |= SMSC_MAC_CSR_TXEN;
smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr);
smsc_write_reg(sc, SMSC_TX_CFG, SMSC_TX_CFG_ON);
/*
* Start RX
*/
sc->sc_mac_csr |= SMSC_MAC_CSR_RXEN;
smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr);
return (0);
init_failed:
smsc_err_printf(sc, "smsc_chip_init failed (err=%d)\n", err);
return (err);
}
