int skl_resume_dsp(struct skl *skl) { struct skl_sst *ctx = skl->skl_sst; int ret; /* if ppcap is not supported return 0 */ if (!skl->ebus.bus.ppcap) return 0; /* enable ppcap interrupt */ snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true); snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true); /* check if DSP 1st boot is done */ if (skl->skl_sst->is_first_boot == true) return 0; /* disable dynamic clock gating during fw and lib download */ ctx->enable_miscbdcge(ctx->dev, false); ret = skl_dsp_wake(ctx->dsp); ctx->enable_miscbdcge(ctx->dev, true); if (ret < 0) return ret; skl_dsp_enable_notification(skl->skl_sst, false); if (skl->cfg.astate_cfg != NULL) { skl_dsp_set_astate_cfg(skl->skl_sst, skl->cfg.astate_cfg->count, skl->cfg.astate_cfg); } return ret; }
int skl_init_dsp(struct skl *skl) { void __iomem *mmio_base; struct hdac_ext_bus *ebus = &skl->ebus; struct hdac_bus *bus = ebus_to_hbus(ebus); int irq = bus->irq; struct skl_dsp_loader_ops loader_ops; int ret; loader_ops.alloc_dma_buf = skl_alloc_dma_buf; loader_ops.free_dma_buf = skl_free_dma_buf; /* enable ppcap interrupt */ snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true); snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true); /* read the BAR of the ADSP MMIO */ mmio_base = pci_ioremap_bar(skl->pci, 4); if (mmio_base == NULL) { dev_err(bus->dev, "ioremap error\n"); return -ENXIO; } ret = skl_sst_dsp_init(bus->dev, mmio_base, irq, skl->fw_name, loader_ops, &skl->skl_sst); if (ret < 0) return ret; skl_dsp_enable_notification(skl->skl_sst, false); dev_dbg(bus->dev, "dsp registration status=%d\n", ret); return ret; }
int skl_resume_dsp(struct skl *skl) { struct skl_sst *ctx = skl->skl_sst; /* if ppcap is not supported return 0 */ if (!skl->ebus.ppcap) return 0; /* enable ppcap interrupt */ snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true); snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true); return skl_dsp_wake(ctx->dsp); }
int skl_suspend_dsp(struct skl *skl) { struct skl_sst *ctx = skl->skl_sst; int ret; /* if ppcap is not supported return 0 */ if (!skl->ebus.bus.ppcap) return 0; ret = skl_dsp_sleep(ctx->dsp); if (ret < 0) return ret; /* disable ppcap interrupt */ snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false); snd_hdac_ext_bus_ppcap_enable(&skl->ebus, false); return 0; }
int skl_resume_dsp(struct skl *skl) { struct skl_sst *ctx = skl->skl_sst; int ret; /* if ppcap is not supported return 0 */ if (!skl->ebus.ppcap) return 0; /* enable ppcap interrupt */ snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true); snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true); ret = skl_dsp_wake(ctx->dsp); if (ret < 0) return ret; skl_dsp_enable_notification(skl->skl_sst, false); return ret; }
int skl_resume_dsp(struct skl *skl) { struct skl_sst *ctx = skl->skl_sst; struct hdac_bus *bus = skl_to_bus(skl); int ret; /* if ppcap is not supported return 0 */ if (!bus->ppcap) return 0; /* enable ppcap interrupt */ snd_hdac_ext_bus_ppcap_enable(bus, true); snd_hdac_ext_bus_ppcap_int_enable(bus, true); /* check if DSP 1st boot is done */ if (skl->skl_sst->is_first_boot) return 0; /* * Disable dynamic clock and power gating during firmware * and library download */ ctx->enable_miscbdcge(ctx->dev, false); ctx->clock_power_gating(ctx->dev, false); ret = skl_dsp_wake(ctx->dsp); ctx->enable_miscbdcge(ctx->dev, true); ctx->clock_power_gating(ctx->dev, true); if (ret < 0) return ret; skl_dsp_enable_notification(skl->skl_sst, false); if (skl->cfg.astate_cfg != NULL) { skl_dsp_set_astate_cfg(skl->skl_sst, skl->cfg.astate_cfg->count, skl->cfg.astate_cfg); } return ret; }
int skl_init_dsp(struct skl *skl) { void __iomem *mmio_base; struct hdac_bus *bus = skl_to_bus(skl); struct skl_dsp_loader_ops loader_ops; int irq = bus->irq; const struct skl_dsp_ops *ops; struct skl_dsp_cores *cores; int ret; /* enable ppcap interrupt */ snd_hdac_ext_bus_ppcap_enable(bus, true); snd_hdac_ext_bus_ppcap_int_enable(bus, true); /* read the BAR of the ADSP MMIO */ mmio_base = pci_ioremap_bar(skl->pci, 4); if (mmio_base == NULL) { dev_err(bus->dev, "ioremap error\n"); return -ENXIO; } ops = skl_get_dsp_ops(skl->pci->device); if (!ops) { ret = -EIO; goto unmap_mmio; } loader_ops = ops->loader_ops(); ret = ops->init(bus->dev, mmio_base, irq, skl->fw_name, loader_ops, &skl->skl_sst); if (ret < 0) goto unmap_mmio; skl->skl_sst->dsp_ops = ops; cores = &skl->skl_sst->cores; cores->count = ops->num_cores; cores->state = kcalloc(cores->count, sizeof(*cores->state), GFP_KERNEL); if (!cores->state) { ret = -ENOMEM; goto unmap_mmio; } cores->usage_count = kcalloc(cores->count, sizeof(*cores->usage_count), GFP_KERNEL); if (!cores->usage_count) { ret = -ENOMEM; goto free_core_state; } dev_dbg(bus->dev, "dsp registration status=%d\n", ret); return 0; free_core_state: kfree(cores->state); unmap_mmio: iounmap(mmio_base); return ret; }