static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) { struct pcm512x_priv *pcm512x = rule->private; struct snd_interval ranges[2]; int frame_size; frame_size = snd_soc_params_to_frame_size(params); if (frame_size < 0) return frame_size; switch (frame_size) { case 32: /* No hole when the frame size is 32. */ return 0; case 48: case 64: /* There is only one hole in the range of supported * rates, but it moves with the frame size. */ memset(ranges, 0, sizeof(ranges)); ranges[0].min = 8000; ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; ranges[1].min = DIV_ROUND_UP(16000000, frame_size); ranges[1].max = 384000; break; default: return -EINVAL; } return snd_interval_ranges(hw_param_interval(params, rule->var), ARRAY_SIZE(ranges), ranges, 0); }
static int rt5616_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_codec *codec = rtd->codec; struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec); unsigned int val_len = 0, val_clk, mask_clk; int pre_div, bclk_ms, frame_size; rt5616->lrck[dai->id] = params_rate(params); pre_div = rl6231_get_clk_info(rt5616->sysclk, rt5616->lrck[dai->id]); if (pre_div < 0) { dev_err(codec->dev, "Unsupported clock setting\n"); return -EINVAL; } frame_size = snd_soc_params_to_frame_size(params); if (frame_size < 0) { dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); return -EINVAL; } bclk_ms = frame_size > 32 ? 1 : 0; rt5616->bclk[dai->id] = rt5616->lrck[dai->id] * (32 << bclk_ms); dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", rt5616->bclk[dai->id], rt5616->lrck[dai->id]); dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", bclk_ms, pre_div, dai->id); switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: break; case SNDRV_PCM_FORMAT_S20_3LE: val_len |= RT5616_I2S_DL_20; break; case SNDRV_PCM_FORMAT_S24_LE: val_len |= RT5616_I2S_DL_24; break; case SNDRV_PCM_FORMAT_S8: val_len |= RT5616_I2S_DL_8; break; default: return -EINVAL; } mask_clk = RT5616_I2S_PD1_MASK; val_clk = pre_div << RT5616_I2S_PD1_SFT; snd_soc_update_bits(codec, RT5616_I2S1_SDP, RT5616_I2S_DL_MASK, val_len); snd_soc_update_bits(codec, RT5616_ADDA_CLK1, mask_clk, val_clk); return 0; }
int snd_soc_params_to_bclk(struct snd_pcm_hw_params *params) { int ret; ret = snd_soc_params_to_frame_size(params); if (ret > 0) return ret * params_rate(params); else return ret; }
static int pcm512x_set_dividers(struct snd_soc_dai *dai, struct snd_pcm_hw_params *params) { struct device *dev = dai->dev; struct snd_soc_codec *codec = dai->codec; struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); unsigned long pllin_rate = 0; unsigned long pll_rate; unsigned long sck_rate; unsigned long mck_rate; unsigned long bclk_rate; unsigned long sample_rate; unsigned long osr_rate; unsigned long dacsrc_rate; int bclk_div; int lrclk_div; int dsp_div; int dac_div; unsigned long dac_rate; int ncp_div; int osr_div; int ret; int idac; int fssp; int gpio; lrclk_div = snd_soc_params_to_frame_size(params); if (lrclk_div == 0) { dev_err(dev, "No LRCLK?\n"); return -EINVAL; } if (!pcm512x->pll_out) { sck_rate = clk_get_rate(pcm512x->sclk); bclk_div = params->rate_den * 64 / lrclk_div; bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div); mck_rate = sck_rate; } else { ret = snd_soc_params_to_bclk(params); if (ret < 0) { dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); return ret; } if (ret == 0) { dev_err(dev, "No BCLK?\n"); return -EINVAL; } bclk_rate = ret; pllin_rate = clk_get_rate(pcm512x->sclk); sck_rate = pcm512x_find_sck(dai, bclk_rate); if (!sck_rate) return -EINVAL; pll_rate = 4 * sck_rate; ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); if (ret != 0) return ret; ret = regmap_write(pcm512x->regmap, PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); if (ret != 0) { dev_err(dev, "Failed to write PLL P: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_PLL_COEFF_1, pcm512x->pll_j); if (ret != 0) { dev_err(dev, "Failed to write PLL J: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); if (ret != 0) { dev_err(dev, "Failed to write PLL D msb: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); if (ret != 0) { dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); if (ret != 0) { dev_err(dev, "Failed to write PLL R: %d\n", ret); return ret; } mck_rate = pcm512x->real_pll; bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); } if (bclk_div > 128) { dev_err(dev, "Failed to find BCLK divider\n"); return -EINVAL; } /* the actual rate */ sample_rate = sck_rate / bclk_div / lrclk_div; osr_rate = 16 * sample_rate; /* run DSP no faster than 50 MHz */ dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); if (dac_rate) { /* the desired clock rate is "compatible" with the pll input * clock, so use that clock as dac input instead of the pll * output clock since the pll will introduce jitter and thus * noise. */ dev_dbg(dev, "using pll input as dac input\n"); ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, PCM512x_SDAC, PCM512x_SDAC_GPIO); if (ret != 0) { dev_err(codec->dev, "Failed to set gpio as dacref: %d\n", ret); return ret; } gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN, PCM512x_GREF, gpio); if (ret != 0) { dev_err(codec->dev, "Failed to set gpio %d as dacin: %d\n", pcm512x->pll_in, ret); return ret; } dacsrc_rate = pllin_rate; } else { /* run DAC no faster than 6144000 Hz */ unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000) / osr_rate; unsigned long sck_mul = sck_rate / osr_rate; for (; dac_mul; dac_mul--) { if (!(sck_mul % dac_mul)) break; } if (!dac_mul) { dev_err(dev, "Failed to find DAC rate\n"); return -EINVAL; } dac_rate = dac_mul * osr_rate; dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", dac_rate, sample_rate); ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, PCM512x_SDAC, PCM512x_SDAC_SCK); if (ret != 0) { dev_err(codec->dev, "Failed to set sck as dacref: %d\n", ret); return ret; } dacsrc_rate = sck_rate; } osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); if (osr_div > 128) { dev_err(dev, "Failed to find OSR divider\n"); return -EINVAL; } dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); if (dac_div > 128) { dev_err(dev, "Failed to find DAC divider\n"); return -EINVAL; } dac_rate = dacsrc_rate / dac_div; ncp_div = DIV_ROUND_CLOSEST(dac_rate, pcm512x_ncp_target(pcm512x, dac_rate)); if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { /* run NCP no faster than 2048000 Hz, but why? */ ncp_div = DIV_ROUND_UP(dac_rate, 2048000); if (ncp_div > 128) { dev_err(dev, "Failed to find NCP divider\n"); return -EINVAL; } } idac = mck_rate / (dsp_div * sample_rate); ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1); if (ret != 0) { dev_err(dev, "Failed to write DSP divider: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1); if (ret != 0) { dev_err(dev, "Failed to write DAC divider: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1); if (ret != 0) { dev_err(dev, "Failed to write NCP divider: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1); if (ret != 0) { dev_err(dev, "Failed to write OSR divider: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_MASTER_CLKDIV_1, bclk_div - 1); if (ret != 0) { dev_err(dev, "Failed to write BCLK divider: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_MASTER_CLKDIV_2, lrclk_div - 1); if (ret != 0) { dev_err(dev, "Failed to write LRCLK divider: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8); if (ret != 0) { dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret); return ret; } ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff); if (ret != 0) { dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret); return ret; } if (sample_rate <= pcm512x_dac_max(pcm512x, 48000)) fssp = PCM512x_FSSP_48KHZ; else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000)) fssp = PCM512x_FSSP_96KHZ; else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000)) fssp = PCM512x_FSSP_192KHZ; else fssp = PCM512x_FSSP_384KHZ; ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE, PCM512x_FSSP, fssp); if (ret != 0) { dev_err(codec->dev, "Failed to set fs speed: %d\n", ret); return ret; } dev_dbg(codec->dev, "DSP divider %d\n", dsp_div); dev_dbg(codec->dev, "DAC divider %d\n", dac_div); dev_dbg(codec->dev, "NCP divider %d\n", ncp_div); dev_dbg(codec->dev, "OSR divider %d\n", osr_div); dev_dbg(codec->dev, "BCK divider %d\n", bclk_div); dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div); dev_dbg(codec->dev, "IDAC %d\n", idac); dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp); return 0; }
static int aic31xx_setup_pll(struct snd_soc_codec *codec, struct snd_pcm_hw_params *params) { struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); int bclk_score = snd_soc_params_to_frame_size(params); int mclk_p = aic31xx->sysclk / aic31xx->p_div; int bclk_n = 0; int match = -1; int i; /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); snd_soc_update_bits(codec, AIC31XX_IFACE2, AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { if (aic31xx_divs[i].rate == params_rate(params) && aic31xx_divs[i].mclk_p == mclk_p) { int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) % snd_soc_params_to_frame_size(params); int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / snd_soc_params_to_frame_size(params); if (s < bclk_score && bn > 0) { match = i; bclk_n = bn; bclk_score = s; } } } if (match == -1) { dev_err(codec->dev, "%s: Sample rate (%u) and format not supported\n", __func__, params_rate(params)); /* See bellow for details how fix this. */ return -EINVAL; } if (bclk_score != 0) { dev_warn(codec->dev, "Can not produce exact bitclock"); /* This is fine if using dsp format, but if using i2s there may be trouble. To fix the issue edit the aic31xx_divs table for your mclk and sample rate. Details can be found from: http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf Section: 5.6 CLOCK Generation and PLL */ } i = match; /* PLL configuration */ snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK, (aic31xx->p_div << 4) | 0x01); snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); snd_soc_write(codec, AIC31XX_PLLDMSB, aic31xx_divs[i].pll_d >> 8); snd_soc_write(codec, AIC31XX_PLLDLSB, aic31xx_divs[i].pll_d & 0xff); /* DAC dividers configuration */ snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK, aic31xx_divs[i].ndac); snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK, aic31xx_divs[i].mdac); snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); /* ADC dividers configuration. Write reset value 1 if not used. */ snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK, aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK, aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr); /* Bit clock divider configuration. */ snd_soc_update_bits(codec, AIC31XX_BCLKN, AIC31XX_PLL_MASK, bclk_n); aic31xx->rate_div_line = i; dev_dbg(codec->dev, "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d, aic31xx->p_div, aic31xx_divs[i].dosr, aic31xx_divs[i].ndac, aic31xx_divs[i].mdac, aic31xx_divs[i].aosr, aic31xx_divs[i].nadc, aic31xx_divs[i].madc, bclk_n); return 0; }
static int aic31xx_setup_pll(struct snd_soc_codec *codec, struct snd_pcm_hw_params *params) { struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); int bclk_n = 0; int i; /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); snd_soc_update_bits(codec, AIC31XX_IFACE2, AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { if (aic31xx_divs[i].rate == params_rate(params) && aic31xx_divs[i].mclk == aic31xx->sysclk) break; } if (i == ARRAY_SIZE(aic31xx_divs)) { dev_err(codec->dev, "%s: Sampling rate %u not supported\n", __func__, params_rate(params)); return -EINVAL; } /* PLL configuration */ snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK, (aic31xx_divs[i].p_val << 4) | 0x01); snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); snd_soc_write(codec, AIC31XX_PLLDMSB, aic31xx_divs[i].pll_d >> 8); snd_soc_write(codec, AIC31XX_PLLDLSB, aic31xx_divs[i].pll_d & 0xff); /* DAC dividers configuration */ snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK, aic31xx_divs[i].ndac); snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK, aic31xx_divs[i].mdac); snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); /* ADC dividers configuration. Write reset value 1 if not used. */ snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK, aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK, aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr); /* Bit clock divider configuration. */ bclk_n = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / snd_soc_params_to_frame_size(params); if (bclk_n == 0) { dev_err(codec->dev, "%s: Not enough BLCK bandwidth\n", __func__); return -EINVAL; } snd_soc_update_bits(codec, AIC31XX_BCLKN, AIC31XX_PLL_MASK, bclk_n); aic31xx->rate_div_line = i; dev_dbg(codec->dev, "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d, aic31xx_divs[i].p_val, aic31xx_divs[i].dosr, aic31xx_divs[i].ndac, aic31xx_divs[i].mdac, aic31xx_divs[i].aosr, aic31xx_divs[i].nadc, aic31xx_divs[i].madc, bclk_n); return 0; }
/* * When the bit clock is input, limit the maximum rate according to the * Serial Clock Ratio Considerations section from the SSC documentation: * * The Transmitter and the Receiver can be programmed to operate * with the clock signals provided on either the TK or RK pins. * This allows the SSC to support many slave-mode data transfers. * In this case, the maximum clock speed allowed on the RK pin is: * - Peripheral clock divided by 2 if Receiver Frame Synchro is input * - Peripheral clock divided by 3 if Receiver Frame Synchro is output * In addition, the maximum clock speed allowed on the TK pin is: * - Peripheral clock divided by 6 if Transmit Frame Synchro is input * - Peripheral clock divided by 2 if Transmit Frame Synchro is output * * When the bit clock is output, limit the rate according to the * SSC divider restrictions. */ static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) { struct atmel_ssc_info *ssc_p = rule->private; struct ssc_device *ssc = ssc_p->ssc; struct snd_interval *i = hw_param_interval(params, rule->var); struct snd_interval t; struct snd_ratnum r = { .den_min = 1, .den_max = 4095, .den_step = 1, }; unsigned int num = 0, den = 0; int frame_size; int mck_div = 2; int ret; frame_size = snd_soc_params_to_frame_size(params); if (frame_size < 0) return frame_size; switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBM_CFS: if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE) && ssc->clk_from_rk_pin) /* Receiver Frame Synchro (i.e. capture) * is output (format is _CFS) and the RK pin * is used for input (format is _CBM_). */ mck_div = 3; break; case SND_SOC_DAIFMT_CBM_CFM: if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK) && !ssc->clk_from_rk_pin) /* Transmit Frame Synchro (i.e. playback) * is input (format is _CFM) and the TK pin * is used for input (format _CBM_ but not * using the RK pin). */ mck_div = 6; break; } switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: r.num = ssc_p->mck_rate / mck_div / frame_size; ret = snd_interval_ratnum(i, 1, &r, &num, &den); if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) { params->rate_num = num; params->rate_den = den; } break; case SND_SOC_DAIFMT_CBM_CFS: case SND_SOC_DAIFMT_CBM_CFM: t.min = 8000; t.max = ssc_p->mck_rate / mck_div / frame_size; t.openmin = t.openmax = 0; t.integer = 0; ret = snd_interval_refine(i, &t); break; default: ret = -EINVAL; break; } return ret; } /*-------------------------------------------------------------------------*\ * DAI functions \*-------------------------------------------------------------------------*/ /* * Startup. Only that one substream allowed in each direction. */ static int atmel_ssc_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct platform_device *pdev = to_platform_device(dai->dev); struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; struct atmel_pcm_dma_params *dma_params; int dir, dir_mask; int ret; pr_debug("atmel_ssc_startup: SSC_SR=0x%x\n", ssc_readl(ssc_p->ssc->regs, SR)); /* Enable PMC peripheral clock for this SSC */ pr_debug("atmel_ssc_dai: Starting clock\n"); clk_enable(ssc_p->ssc->clk); ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk); /* Reset the SSC unless initialized to keep it in a clean state */ if (!ssc_p->initialized) ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { dir = 0; dir_mask = SSC_DIR_MASK_PLAYBACK; } else { dir = 1; dir_mask = SSC_DIR_MASK_CAPTURE; } ret = snd_pcm_hw_rule_add(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, atmel_ssc_hw_rule_rate, ssc_p, SNDRV_PCM_HW_PARAM_FRAME_BITS, SNDRV_PCM_HW_PARAM_CHANNELS, -1); if (ret < 0) { dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret); return ret; } dma_params = &ssc_dma_params[pdev->id][dir]; dma_params->ssc = ssc_p->ssc; dma_params->substream = substream; ssc_p->dma_params[dir] = dma_params; snd_soc_dai_set_dma_data(dai, substream, dma_params); spin_lock_irq(&ssc_p->lock); if (ssc_p->dir_mask & dir_mask) { spin_unlock_irq(&ssc_p->lock); return -EBUSY; } ssc_p->dir_mask |= dir_mask; spin_unlock_irq(&ssc_p->lock); return 0; } /* * Shutdown. Clear DMA parameters and shutdown the SSC if there * are no other substreams open. */ static void atmel_ssc_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct platform_device *pdev = to_platform_device(dai->dev); struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; struct atmel_pcm_dma_params *dma_params; int dir, dir_mask; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) dir = 0; else dir = 1; dma_params = ssc_p->dma_params[dir]; if (dma_params != NULL) { dma_params->ssc = NULL; dma_params->substream = NULL; ssc_p->dma_params[dir] = NULL; } dir_mask = 1 << dir; spin_lock_irq(&ssc_p->lock); ssc_p->dir_mask &= ~dir_mask; if (!ssc_p->dir_mask) { if (ssc_p->initialized) { free_irq(ssc_p->ssc->irq, ssc_p); ssc_p->initialized = 0; } /* Reset the SSC */ ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); /* Clear the SSC dividers */ ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0; } spin_unlock_irq(&ssc_p->lock); /* Shutdown the SSC clock. */ pr_debug("atmel_ssc_dai: Stopping clock\n"); clk_disable(ssc_p->ssc->clk); } /* * Record the DAI format for use in hw_params(). */ static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) { struct platform_device *pdev = to_platform_device(cpu_dai->dev); struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; ssc_p->daifmt = fmt; return 0; } /* * Record SSC clock dividers for use in hw_params(). */ static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, int div_id, int div) { struct platform_device *pdev = to_platform_device(cpu_dai->dev); struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; switch (div_id) { case ATMEL_SSC_CMR_DIV: /* * The same master clock divider is used for both * transmit and receive, so if a value has already * been set, it must match this value. */ if (ssc_p->dir_mask != (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE)) ssc_p->cmr_div = div; else if (ssc_p->cmr_div == 0) ssc_p->cmr_div = div; else if (div != ssc_p->cmr_div) return -EBUSY; break; case ATMEL_SSC_TCMR_PERIOD: ssc_p->tcmr_period = div; break; case ATMEL_SSC_RCMR_PERIOD: ssc_p->rcmr_period = div; break; default: return -EINVAL; } return 0; } /* * Configure the SSC. */ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct platform_device *pdev = to_platform_device(dai->dev); int id = pdev->id; struct atmel_ssc_info *ssc_p = &ssc_info[id]; struct ssc_device *ssc = ssc_p->ssc; struct atmel_pcm_dma_params *dma_params; int dir, channels, bits; u32 tfmr, rfmr, tcmr, rcmr; int ret; int fslen, fslen_ext; /* * Currently, there is only one set of dma params for * each direction. If more are added, this code will * have to be changed to select the proper set. */ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) dir = 0; else dir = 1; dma_params = ssc_p->dma_params[dir]; channels = params_channels(params); /* * Determine sample size in bits and the PDC increment. */ switch (params_format(params)) { case SNDRV_PCM_FORMAT_S8: bits = 8; dma_params->pdc_xfer_size = 1; break; case SNDRV_PCM_FORMAT_S16_LE: bits = 16; dma_params->pdc_xfer_size = 2; break; case SNDRV_PCM_FORMAT_S24_LE: bits = 24; dma_params->pdc_xfer_size = 4; break; case SNDRV_PCM_FORMAT_S32_LE: bits = 32; dma_params->pdc_xfer_size = 4; break; default: printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format"); return -EINVAL; } /* * Compute SSC register settings. */ switch (ssc_p->daifmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) { case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS: /* * I2S format, SSC provides BCLK and LRC clocks. * * The SSC transmit and receive clocks are generated * from the MCK divider, and the BCLK signal * is output on the SSC TK line. */ if (bits > 16 && !ssc->pdata->has_fslen_ext) { dev_err(dai->dev, "sample size %d is too large for SSC device\n", bits); return -EINVAL; } fslen_ext = (bits - 1) / 16; fslen = (bits - 1) % 16; rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) | SSC_BF(RCMR_STTDLY, START_DELAY) | SSC_BF(RCMR_START, SSC_START_FALLING_RF) | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | SSC_BF(RCMR_CKS, SSC_CKS_DIV); rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext) | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) | SSC_BF(RFMR_FSLEN, fslen) | SSC_BF(RFMR_DATNB, (channels - 1)) | SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_LOOP, 0) | SSC_BF(RFMR_DATLEN, (bits - 1)); tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) | SSC_BF(TCMR_STTDLY, START_DELAY) | SSC_BF(TCMR_START, SSC_START_FALLING_RF) | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) | SSC_BF(TCMR_CKS, SSC_CKS_DIV); tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext) | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(TFMR_FSDEN, 0) | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) | SSC_BF(TFMR_FSLEN, fslen) | SSC_BF(TFMR_DATNB, (channels - 1)) | SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATDEF, 0) | SSC_BF(TFMR_DATLEN, (bits - 1)); break; case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM: /* I2S format, CODEC supplies BCLK and LRC clocks. */ rcmr = SSC_BF(RCMR_PERIOD, 0) | SSC_BF(RCMR_STTDLY, START_DELAY) | SSC_BF(RCMR_START, SSC_START_FALLING_RF) | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? SSC_CKS_PIN : SSC_CKS_CLOCK); rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) | SSC_BF(RFMR_FSLEN, 0) | SSC_BF(RFMR_DATNB, (channels - 1)) | SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_LOOP, 0) | SSC_BF(RFMR_DATLEN, (bits - 1)); tcmr = SSC_BF(TCMR_PERIOD, 0) | SSC_BF(TCMR_STTDLY, START_DELAY) | SSC_BF(TCMR_START, SSC_START_FALLING_RF) | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ? SSC_CKS_CLOCK : SSC_CKS_PIN); tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(TFMR_FSDEN, 0) | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) | SSC_BF(TFMR_FSLEN, 0) | SSC_BF(TFMR_DATNB, (channels - 1)) | SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATDEF, 0) | SSC_BF(TFMR_DATLEN, (bits - 1)); break; case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS: /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */ if (bits > 16 && !ssc->pdata->has_fslen_ext) { dev_err(dai->dev, "sample size %d is too large for SSC device\n", bits); return -EINVAL; } fslen_ext = (bits - 1) / 16; fslen = (bits - 1) % 16; rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) | SSC_BF(RCMR_STTDLY, START_DELAY) | SSC_BF(RCMR_START, SSC_START_FALLING_RF) | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? SSC_CKS_PIN : SSC_CKS_CLOCK); rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext) | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) | SSC_BF(RFMR_FSLEN, fslen) | SSC_BF(RFMR_DATNB, (channels - 1)) | SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_LOOP, 0) | SSC_BF(RFMR_DATLEN, (bits - 1)); tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) | SSC_BF(TCMR_STTDLY, START_DELAY) | SSC_BF(TCMR_START, SSC_START_FALLING_RF) | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ? SSC_CKS_CLOCK : SSC_CKS_PIN); tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext) | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE) | SSC_BF(TFMR_FSDEN, 0) | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) | SSC_BF(TFMR_FSLEN, fslen) | SSC_BF(TFMR_DATNB, (channels - 1)) | SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATDEF, 0) | SSC_BF(TFMR_DATLEN, (bits - 1)); break; case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS: /* * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. * * The SSC transmit and receive clocks are generated from the * MCK divider, and the BCLK signal is output * on the SSC TK line. */ rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) | SSC_BF(RCMR_STTDLY, 1) | SSC_BF(RCMR_START, SSC_START_RISING_RF) | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | SSC_BF(RCMR_CKS, SSC_CKS_DIV); rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE) | SSC_BF(RFMR_FSLEN, 0) | SSC_BF(RFMR_DATNB, (channels - 1)) | SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_LOOP, 0) | SSC_BF(RFMR_DATLEN, (bits - 1)); tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) | SSC_BF(TCMR_STTDLY, 1) | SSC_BF(TCMR_START, SSC_START_RISING_RF) | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) | SSC_BF(TCMR_CKS, SSC_CKS_DIV); tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(TFMR_FSDEN, 0) | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE) | SSC_BF(TFMR_FSLEN, 0) | SSC_BF(TFMR_DATNB, (channels - 1)) | SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATDEF, 0) | SSC_BF(TFMR_DATLEN, (bits - 1)); break; case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM: /* * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks. * * Data is transferred on first BCLK after LRC pulse rising * edge.If stereo, the right channel data is contiguous with * the left channel data. */ rcmr = SSC_BF(RCMR_PERIOD, 0) | SSC_BF(RCMR_STTDLY, START_DELAY) | SSC_BF(RCMR_START, SSC_START_RISING_RF) | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? SSC_CKS_PIN : SSC_CKS_CLOCK); rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) | SSC_BF(RFMR_FSLEN, 0) | SSC_BF(RFMR_DATNB, (channels - 1)) | SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_LOOP, 0) | SSC_BF(RFMR_DATLEN, (bits - 1)); tcmr = SSC_BF(TCMR_PERIOD, 0) | SSC_BF(TCMR_STTDLY, START_DELAY) | SSC_BF(TCMR_START, SSC_START_RISING_RF) | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? SSC_CKS_CLOCK : SSC_CKS_PIN); tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(TFMR_FSDEN, 0) | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) | SSC_BF(TFMR_FSLEN, 0) | SSC_BF(TFMR_DATNB, (channels - 1)) | SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATDEF, 0) | SSC_BF(TFMR_DATLEN, (bits - 1)); break; default: printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n", ssc_p->daifmt); return -EINVAL; } pr_debug("atmel_ssc_hw_params: " "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", rcmr, rfmr, tcmr, tfmr); if (!ssc_p->initialized) { if (!ssc_p->ssc->pdata->use_dma) { ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0); ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0); ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0); ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0); ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0); ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0); ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0); ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0); } ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0, ssc_p->name, ssc_p); if (ret < 0) { printk(KERN_WARNING "atmel_ssc_dai: request_irq failure\n"); pr_debug("Atmel_ssc_dai: Stoping clock\n"); clk_disable(ssc_p->ssc->clk); return ret; } ssc_p->initialized = 1; } /* set SSC clock mode register */ ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div); /* set receive clock mode and format */ ssc_writel(ssc_p->ssc->regs, RCMR, rcmr); ssc_writel(ssc_p->ssc->regs, RFMR, rfmr); /* set transmit clock mode and format */ ssc_writel(ssc_p->ssc->regs, TCMR, tcmr); ssc_writel(ssc_p->ssc->regs, TFMR, tfmr); pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n"); return 0; } static int atmel_ssc_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct platform_device *pdev = to_platform_device(dai->dev); struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; struct atmel_pcm_dma_params *dma_params; int dir; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) dir = 0; else dir = 1; dma_params = ssc_p->dma_params[dir]; ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error); pr_debug("%s enabled SSC_SR=0x%08x\n", dir ? "receive" : "transmit", ssc_readl(ssc_p->ssc->regs, SR)); return 0; } static int atmel_ssc_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { struct platform_device *pdev = to_platform_device(dai->dev); struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; struct atmel_pcm_dma_params *dma_params; int dir; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) dir = 0; else dir = 1; dma_params = ssc_p->dma_params[dir]; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable); break; default: ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); break; } return 0; } #ifdef CONFIG_PM static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai) { struct atmel_ssc_info *ssc_p; struct platform_device *pdev = to_platform_device(cpu_dai->dev); if (!cpu_dai->active) return 0; ssc_p = &ssc_info[pdev->id]; /* Save the status register before disabling transmit and receive */ ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS)); /* Save the current interrupt mask, then disable unmasked interrupts */ ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR); ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr); ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR); ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR); ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR); ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR); ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR); return 0; } static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai) { struct atmel_ssc_info *ssc_p; struct platform_device *pdev = to_platform_device(cpu_dai->dev); u32 cr; if (!cpu_dai->active) return 0; ssc_p = &ssc_info[pdev->id]; /* restore SSC register settings */ ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr); ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr); ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr); ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr); ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr); /* re-enable interrupts */ ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr); /* Re-enable receive and transmit as appropriate */ cr = 0; cr |= (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0; cr |= (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0; ssc_writel(ssc_p->ssc->regs, CR, cr); return 0; } #else /* CONFIG_PM */ # define atmel_ssc_suspend NULL # define atmel_ssc_resume NULL #endif /* CONFIG_PM */ #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) static const struct snd_soc_dai_ops atmel_ssc_dai_ops = { .startup = atmel_ssc_startup, .shutdown = atmel_ssc_shutdown, .prepare = atmel_ssc_prepare, .trigger = atmel_ssc_trigger, .hw_params = atmel_ssc_hw_params, .set_fmt = atmel_ssc_set_dai_fmt, .set_clkdiv = atmel_ssc_set_dai_clkdiv, }; static struct snd_soc_dai_driver atmel_ssc_dai = { .suspend = atmel_ssc_suspend, .resume = atmel_ssc_resume, .playback = { .channels_min = 1, .channels_max = 2, .rates = SNDRV_PCM_RATE_CONTINUOUS, .rate_min = 8000, .rate_max = 384000, .formats = ATMEL_SSC_FORMATS,}, .capture = { .channels_min = 1, .channels_max = 2, .rates = SNDRV_PCM_RATE_CONTINUOUS, .rate_min = 8000, .rate_max = 384000, .formats = ATMEL_SSC_FORMATS,}, .ops = &atmel_ssc_dai_ops,